Improvement in top-gate MoS₂ transistor performance due to high quality backside Al₂O₃ layer

A high quality Al₂O₃ layer is developed to achieve high performance in top-gate MoS₂ transistors. Compared with top-gate MoS₂ field effect transistors on a SiO₂ layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al₂O₃ layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ∼69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μ_o) of 145 cm²/V·s, indicating a positive influence on top-gate device performance even without any backside bias.