TY - GEN
T1 - Improving defectivity for III-V CMP processes for <10 nm technology nodes
AU - Teugels, Lieve
AU - Ong, Patrick
AU - Boccardi, Guillaume
AU - Waldron, Niamh
AU - Ansar, Sheikh
AU - Siebert, Joerg Max
AU - Leunissen, Leonardus A.H.
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2015/1/20
Y1 - 2015/1/20
N2 - III-V high mobility channel materials are being considered for advanced devices beyond the 10 nm technology node. For pMOS devices, Ge and SiGe have already been shown to be viable candidates [1,2] while for nMOS devices our focus lies on III-V materials such as InP and InGaAs. For the integration of III-V channel materials, several approaches are being explored: the aspect ratio trapping (ART) method and hetero-epitaxy of III-V compound semiconductors on blanket Si using strain-relaxed buffer layers. This paper focuses on reducing the defectivity of the III-V layers during CMP steps needed for either approach. We show that the use of an improved pad/slurry combination can significantly reduce the CMP-induced damage to the InP fins in the ART approach and can achieve a post-CMP roughness r.m.s. of InGaAs SRB layers of ∼0.7 nm.
AB - III-V high mobility channel materials are being considered for advanced devices beyond the 10 nm technology node. For pMOS devices, Ge and SiGe have already been shown to be viable candidates [1,2] while for nMOS devices our focus lies on III-V materials such as InP and InGaAs. For the integration of III-V channel materials, several approaches are being explored: the aspect ratio trapping (ART) method and hetero-epitaxy of III-V compound semiconductors on blanket Si using strain-relaxed buffer layers. This paper focuses on reducing the defectivity of the III-V layers during CMP steps needed for either approach. We show that the use of an improved pad/slurry combination can significantly reduce the CMP-induced damage to the InP fins in the ART approach and can achieve a post-CMP roughness r.m.s. of InGaAs SRB layers of ∼0.7 nm.
UR - https://www.scopus.com/pages/publications/84925379598
U2 - 10.1109/ICPT.2014.7017234
DO - 10.1109/ICPT.2014.7017234
M3 - Conference proceeding
AN - SCOPUS:84925379598
T3 - ICPT 2014 - Proceedings of International Conference on Planarization/CMP Technology 2014
SP - 15
EP - 17
BT - ICPT 2014 - Proceedings of International Conference on Planarization/CMP Technology 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th International Conference on Planarization/CMP Technology, ICPT 2014
Y2 - 19 November 2014 through 21 November 2014
ER -