Investigation of critical interfaces in few-layer MoS₂ field effect transistors with high-k dielectrics

In this work, few-layer MOS₂ FET-based devices were fabricated using top and bottom high-k dielectrics (Al₂O₃ and/or HfO₂). Frequency-dependent C-V data of top-gate FETs shows dispersion in both the depletion and accumulation regions for the MoS₂ devices signifying electrically active interface and possible border traps. Also, metal contact deposition conditions and sulfur treatments on MoS₂ for source and drain determined that ultra high vacuum deposited metals were superior to those deposited only under high vacuum, and the sulfur treatment coupled with a forming gas anneal provides the lowest contact resistance (∼kΩ-μm). With Al₂O₃ as the bottom-gate dielectric layer, a positive influence on HfO₂ top-gate FET performance was achieved-even without any backside bias-because the top-gate intrinsic mobility and subthreshold slope were improved compared to SiO₂ or HfO₂ as back gate dielectric. Furthermore, a forming gas anneal is found to enhance device performance due to a reduction in charge trap density at dielectric interfacial regions, and improved metal contact formation.