Junction architectures for planar devices

B. J. Pawlak; R. Duffy; T. Hoffman; S. Severi; S. B. Felch; P. Eyben; B. Van Daele; W. Vandervorst; R. Lander

doi:10.1149/1.2727420

Junction architectures for planar devices

B. J. Pawlak
, R. Duffy
, T. Hoffman
, S. Severi
, S. B. Felch
, P. Eyben
, B. Van Daele
, W. Vandervorst
, R. Lander

NXP Semiconductors
Interuniversitair Micro-Elektronica Centrum
Applied Materials Incorporated

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

Requirements, main challenges and approaches for ultra-shallow junction formation for planar bulk transistors with gate length in the sub-40 nm regime are discussed. In case of the conventional rapid thermal annealing, addition of the pre-amorphization and F or C coimplants is demonstrated to significantly improve short channel effect control. Another way to improve junction activation and suppress dopant diffusion is to use ion implantation in combination with alternative types of activation methods: low temperature solid phase epitaxial regrowth or high temperature sub-melt laser. All junction formation technologies are investigated on blanket wafers and they are implemented in devices.

Original language	English
Title of host publication	ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS
Subtitle of host publication	New Materials, Processes and Equipment, 3
Publisher	Electrochemical Society Inc.
Pages	351-364
Number of pages	14
Edition	1
ISBN (Electronic)	9781566775502
ISBN (Print)	9781566775502
DOIs	https://doi.org/10.1149/1.2727420
Publication status	Published - 2007
Externally published	Yes
Event	International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 - 211th ECS Meeting - Chicago, IL, United States Duration: 6 May 2007 → 10 May 2007

Publication series

Name	ECS Transactions
Number	1
Volume	6
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Conference

Conference	International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 - 211th ECS Meeting
Country/Territory	United States
City	Chicago, IL
Period	6/05/07 → 10/05/07

Access to Document

10.1149/1.2727420

Cite this

Pawlak, B. J., Duffy, R., Hoffman, T., Severi, S., Felch, S. B., Eyben, P., Van Daele, B., Vandervorst, W., & Lander, R. (2007). Junction architectures for planar devices. In ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 (1 ed., pp. 351-364). (ECS Transactions; Vol. 6, No. 1). Electrochemical Society Inc.. https://doi.org/10.1149/1.2727420

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title = "Junction architectures for planar devices",

abstract = "Requirements, main challenges and approaches for ultra-shallow junction formation for planar bulk transistors with gate length in the sub-40 nm regime are discussed. In case of the conventional rapid thermal annealing, addition of the pre-amorphization and F or C coimplants is demonstrated to significantly improve short channel effect control. Another way to improve junction activation and suppress dopant diffusion is to use ion implantation in combination with alternative types of activation methods: low temperature solid phase epitaxial regrowth or high temperature sub-melt laser. All junction formation technologies are investigated on blanket wafers and they are implemented in devices.",

author = "Pawlak, \{B. J.\} and R. Duffy and T. Hoffman and S. Severi and Felch, \{S. B.\} and P. Eyben and \{Van Daele\}, B. and W. Vandervorst and R. Lander",

year = "2007",

doi = "10.1149/1.2727420",

language = "English",

isbn = "9781566775502",

series = "ECS Transactions",

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booktitle = "ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS",

address = "United States",

edition = "1",

note = "International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 - 211th ECS Meeting ; Conference date: 06-05-2007 Through 10-05-2007",

}

Pawlak, BJ, Duffy, R, Hoffman, T, Severi, S, Felch, SB, Eyben, P, Van Daele, B, Vandervorst, W & Lander, R 2007, Junction architectures for planar devices. in ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3. 1 edn, ECS Transactions, no. 1, vol. 6, Electrochemical Society Inc., pp. 351-364, International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 - 211th ECS Meeting, Chicago, IL, United States, 6/05/07. https://doi.org/10.1149/1.2727420

Junction architectures for planar devices. / Pawlak, B. J.; Duffy, R.; Hoffman, T. et al.
ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3. 1. ed. Electrochemical Society Inc., 2007. p. 351-364 (ECS Transactions; Vol. 6, No. 1).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

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AU - Pawlak, B. J.

AU - Duffy, R.

AU - Hoffman, T.

AU - Severi, S.

AU - Felch, S. B.

AU - Eyben, P.

AU - Van Daele, B.

AU - Vandervorst, W.

AU - Lander, R.

PY - 2007

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AB - Requirements, main challenges and approaches for ultra-shallow junction formation for planar bulk transistors with gate length in the sub-40 nm regime are discussed. In case of the conventional rapid thermal annealing, addition of the pre-amorphization and F or C coimplants is demonstrated to significantly improve short channel effect control. Another way to improve junction activation and suppress dopant diffusion is to use ion implantation in combination with alternative types of activation methods: low temperature solid phase epitaxial regrowth or high temperature sub-melt laser. All junction formation technologies are investigated on blanket wafers and they are implemented in devices.

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DO - 10.1149/1.2727420

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BT - ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS

PB - Electrochemical Society Inc.

T2 - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3 - 211th ECS Meeting

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ER -

Pawlak BJ, Duffy R, Hoffman T, Severi S, Felch SB, Eyben P et al. Junction architectures for planar devices. In ECS Transactions - International Symposium on Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 3. 1 ed. Electrochemical Society Inc. 2007. p. 351-364. (ECS Transactions; 1). doi: 10.1149/1.2727420

Junction architectures for planar devices

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