Junction engineering and modeling for advanced CMOS technologies

C. C. Wang; T. Y. Huang; C. H. Diaz; C. H. Wang; Ray Duffy; N. E.B. Cowern; Peter B. Griffin

doi:10.1109/SISPAD.2003.1233685

Junction engineering and modeling for advanced CMOS technologies

C. C. Wang
, T. Y. Huang
, C. H. Diaz
, C. H. Wang
, Ray Duffy
, N. E.B. Cowern
, Peter B. Griffin

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

This paper discusses an integrated modeling approach for diffusion profiles in advanced CMOS technologies. First, for USJ (Ultra-Shallow Junction) arsenic modeling, in addition to a fully-coupled model with implant damage, amorphous layer formation which depends on the Frenkel pair concentration and evolution of (311) defects and dislocation loops based on EOR (End of Range) defects are also used. Secondly, in order to improve polysilicon activation, a hybrid (arsenic + phosphorus) Source/Drain is used for NMOS. We also address the calibration of the hybrid Source/Drain for with various anneal temperatures. It is shown that modeling of the hybrid Source/Drain profile can be achieved by optimization of the dopant's Fermi level dependent diffusivity and the initial value of the point defect concentration in the equilibrium state. Finally, uphill diffusion at low anneal temperature is observed for BF2 USJ and is enhanced with Ge pre-implants. It is caused by a steep interstitial gradient created by preamorphisation and EOR damage, ultra-shallow boron profile, and boron long-hop diffusion. A BIC (Boron-Interstitial Cluster) model is employed to model boron diffusion after a spike RTA at both extension and S/D regions.

Original language	English
Title of host publication	SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	255-258
Number of pages	4
ISBN (Electronic)	0780378261
DOIs	https://doi.org/10.1109/SISPAD.2003.1233685
Publication status	Published - 2003
Externally published	Yes
Event	2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003 - Boston, United States Duration: 3 Sep 2003 → 5 Sep 2003

Publication series

Name	International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume	2003-January

Conference

Conference	2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003
Country/Territory	United States
City	Boston
Period	3/09/03 → 5/09/03

Keywords

Amorphous materials
Annealing
Boron
Calibration
CMOS technology
Implants
MOS devices
Semiconductor device modeling
Semiconductor process modeling
Temperature

Access to Document

10.1109/SISPAD.2003.1233685

Cite this

Wang, C. C., Huang, T. Y., Diaz, C. H., Wang, C. H., Duffy, R., Cowern, N. E. B., & Griffin, P. B. (2003). Junction engineering and modeling for advanced CMOS technologies. In SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices (pp. 255-258). Article 1233685 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2003-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SISPAD.2003.1233685

Wang, C. C. ; Huang, T. Y. ; Diaz, C. H. et al. / Junction engineering and modeling for advanced CMOS technologies. SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 255-258 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).

@inbook{a1e4b0c2c0d84e4ea1c647c3f8682e9e,

title = "Junction engineering and modeling for advanced CMOS technologies",

abstract = "This paper discusses an integrated modeling approach for diffusion profiles in advanced CMOS technologies. First, for USJ (Ultra-Shallow Junction) arsenic modeling, in addition to a fully-coupled model with implant damage, amorphous layer formation which depends on the Frenkel pair concentration and evolution of (311) defects and dislocation loops based on EOR (End of Range) defects are also used. Secondly, in order to improve polysilicon activation, a hybrid (arsenic + phosphorus) Source/Drain is used for NMOS. We also address the calibration of the hybrid Source/Drain for with various anneal temperatures. It is shown that modeling of the hybrid Source/Drain profile can be achieved by optimization of the dopant's Fermi level dependent diffusivity and the initial value of the point defect concentration in the equilibrium state. Finally, uphill diffusion at low anneal temperature is observed for BF2 USJ and is enhanced with Ge pre-implants. It is caused by a steep interstitial gradient created by preamorphisation and EOR damage, ultra-shallow boron profile, and boron long-hop diffusion. A BIC (Boron-Interstitial Cluster) model is employed to model boron diffusion after a spike RTA at both extension and S/D regions.",

keywords = "Amorphous materials, Annealing, Boron, Calibration, CMOS technology, Implants, MOS devices, Semiconductor device modeling, Semiconductor process modeling, Temperature",

author = "Wang, \{C. C.\} and Huang, \{T. Y.\} and Diaz, \{C. H.\} and Wang, \{C. H.\} and Ray Duffy and Cowern, \{N. E.B.\} and Griffin, \{Peter B.\}",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003 ; Conference date: 03-09-2003 Through 05-09-2003",

year = "2003",

doi = "10.1109/SISPAD.2003.1233685",

language = "English",

series = "International Conference on Simulation of Semiconductor Processes and Devices, SISPAD",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "255--258",

booktitle = "SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices",

address = "United States",

}

Wang, CC, Huang, TY, Diaz, CH, Wang, CH, Duffy, R, Cowern, NEB & Griffin, PB 2003, Junction engineering and modeling for advanced CMOS technologies. in SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices., 1233685, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, vol. 2003-January, Institute of Electrical and Electronics Engineers Inc., pp. 255-258, 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003, Boston, United States, 3/09/03. https://doi.org/10.1109/SISPAD.2003.1233685

Junction engineering and modeling for advanced CMOS technologies. / Wang, C. C.; Huang, T. Y.; Diaz, C. H. et al.
SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices. Institute of Electrical and Electronics Engineers Inc., 2003. p. 255-258 1233685 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2003-January).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

TY - CHAP

T1 - Junction engineering and modeling for advanced CMOS technologies

AU - Wang, C. C.

AU - Huang, T. Y.

AU - Diaz, C. H.

AU - Wang, C. H.

AU - Duffy, Ray

AU - Cowern, N. E.B.

AU - Griffin, Peter B.

PY - 2003

Y1 - 2003

N2 - This paper discusses an integrated modeling approach for diffusion profiles in advanced CMOS technologies. First, for USJ (Ultra-Shallow Junction) arsenic modeling, in addition to a fully-coupled model with implant damage, amorphous layer formation which depends on the Frenkel pair concentration and evolution of (311) defects and dislocation loops based on EOR (End of Range) defects are also used. Secondly, in order to improve polysilicon activation, a hybrid (arsenic + phosphorus) Source/Drain is used for NMOS. We also address the calibration of the hybrid Source/Drain for with various anneal temperatures. It is shown that modeling of the hybrid Source/Drain profile can be achieved by optimization of the dopant's Fermi level dependent diffusivity and the initial value of the point defect concentration in the equilibrium state. Finally, uphill diffusion at low anneal temperature is observed for BF2 USJ and is enhanced with Ge pre-implants. It is caused by a steep interstitial gradient created by preamorphisation and EOR damage, ultra-shallow boron profile, and boron long-hop diffusion. A BIC (Boron-Interstitial Cluster) model is employed to model boron diffusion after a spike RTA at both extension and S/D regions.

AB - This paper discusses an integrated modeling approach for diffusion profiles in advanced CMOS technologies. First, for USJ (Ultra-Shallow Junction) arsenic modeling, in addition to a fully-coupled model with implant damage, amorphous layer formation which depends on the Frenkel pair concentration and evolution of (311) defects and dislocation loops based on EOR (End of Range) defects are also used. Secondly, in order to improve polysilicon activation, a hybrid (arsenic + phosphorus) Source/Drain is used for NMOS. We also address the calibration of the hybrid Source/Drain for with various anneal temperatures. It is shown that modeling of the hybrid Source/Drain profile can be achieved by optimization of the dopant's Fermi level dependent diffusivity and the initial value of the point defect concentration in the equilibrium state. Finally, uphill diffusion at low anneal temperature is observed for BF2 USJ and is enhanced with Ge pre-implants. It is caused by a steep interstitial gradient created by preamorphisation and EOR damage, ultra-shallow boron profile, and boron long-hop diffusion. A BIC (Boron-Interstitial Cluster) model is employed to model boron diffusion after a spike RTA at both extension and S/D regions.

KW - Amorphous materials

KW - Annealing

KW - Boron

KW - Calibration

KW - CMOS technology

KW - Implants

KW - MOS devices

KW - Semiconductor device modeling

KW - Semiconductor process modeling

KW - Temperature

UR - https://www.scopus.com/pages/publications/84943244774

U2 - 10.1109/SISPAD.2003.1233685

DO - 10.1109/SISPAD.2003.1233685

M3 - Chapter

AN - SCOPUS:84943244774

T3 - International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

SP - 255

EP - 258

BT - SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2003

Y2 - 3 September 2003 through 5 September 2003

ER -

Wang CC, Huang TY, Diaz CH, Wang CH, Duffy R, Cowern NEB et al. Junction engineering and modeling for advanced CMOS technologies. In SISPAD 2003 - 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices. Institute of Electrical and Electronics Engineers Inc. 2003. p. 255-258. 1233685. (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). doi: 10.1109/SISPAD.2003.1233685

Junction engineering and modeling for advanced CMOS technologies

Abstract

Publication series

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Keywords

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