Junctionless gate-All-Around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

  • A. Veloso
  • , B. Parvais
  • , P. Matagne
  • , E. Simoen
  • , T. Huynh-Bao
  • , V. Paraschiv
  • , E. Vecchio
  • , K. Devriendt
  • , E. Rosseel
  • , M. Ercken
  • , B. T. Chan
  • , C. Delvaux
  • , E. Altamirano-Sanchez
  • , J. J. Versluijs
  • , Z. Tao
  • , S. Suhard
  • , S. Brus
  • , A. Sibaja-Hernandez
  • , N. Waldron
  • , P. Lagrain
    • O. Richard, H. Bender, A. Chasin, B. Kaczer, T. Ivanov, S. Ramesh, K. De Meyer, J. Ryckaert, N. Collaert, A. Thean

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

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