TY - GEN
T1 - LDD depletion effects in thin-BOX FDSOI devices with a ground plane
AU - Yan, R.
AU - Duane, R.
AU - Razavi, P.
AU - Afzalian, A.
AU - Ferain, I.
AU - Lee, C. W.
AU - Dehdashti-Akhavan, N.
AU - Bourdelle, K.
AU - Nguyen, B. Y.
AU - Colinge, J. P.
PY - 2009
Y1 - 2009
N2 - In this paper, we analyze LDD depletion effects in Fully-Depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15nm.
AB - In this paper, we analyze LDD depletion effects in Fully-Depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15nm.
UR - https://www.scopus.com/pages/publications/72449188736
U2 - 10.1109/SOI.2009.5318771
DO - 10.1109/SOI.2009.5318771
M3 - Conference proceeding
AN - SCOPUS:72449188736
SN - 9781424452323
T3 - Proceedings - IEEE International SOI Conference
BT - 2009 IEEE International SOI Conference
T2 - 2009 IEEE International SOI Conference
Y2 - 5 October 2009 through 8 October 2009
ER -