LDD depletion effects in thin-BOX FDSOI devices with a ground plane

  • R. Yan
  • , R. Duane
  • , P. Razavi
  • , A. Afzalian
  • , I. Ferain
  • , C. W. Lee
  • , N. Dehdashti-Akhavan
  • , K. Bourdelle
  • , B. Y. Nguyen
  • , J. P. Colinge

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

In this paper, we analyze LDD depletion effects in Fully-Depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15nm.

Original languageEnglish
Title of host publication2009 IEEE International SOI Conference
DOIs
Publication statusPublished - 2009
Event2009 IEEE International SOI Conference - Foster City, CA, United States
Duration: 5 Oct 20098 Oct 2009

Publication series

NameProceedings - IEEE International SOI Conference
ISSN (Print)1078-621X

Conference

Conference2009 IEEE International SOI Conference
Country/TerritoryUnited States
CityFoster City, CA
Period5/10/098/10/09

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