TY - CHAP
T1 - Low cost error recovery in delay-intolerant wireless sensor networks
AU - Agarwal, Rachit
AU - Popovici, Emanuel M.
AU - Sala, Massimiliano
AU - O'Flynn, Brendan
PY - 2007
Y1 - 2007
N2 - Transmission efficiency of Wireless Sensor Networks (WSN) is lower than that of conventional networks due to frequent propagation errors. In light of specific features and diverse applications of WSN, common assumptions from communication systems may not hold true and efficient application-specific protocols can be formulated. In this paper, we demonstrate this based on an interesting observation related to shortened Reed-Solomon (RS) codes for packet reliability in WSN. We show that multiple instances (γ) of RS codes defined on a smaller alphabet combined with interleaving result in smaller resource usage while the performance exceeds the benefits of a shortened RS code defined over a larger alphabet. In particular, the proposed scheme can have an error correction capability of up to γ times larger that for the conventional RS scheme without changing the rate of the code with much lower power, timing and memory requirements. Implementation results on 25mm motes developed by Tyndall National Institute show that such a scheme is 43% more power efficient compared to RS scheme with same code rate. Besides, such an approach results in 44% faster computations and 53% reduction in memory required.
AB - Transmission efficiency of Wireless Sensor Networks (WSN) is lower than that of conventional networks due to frequent propagation errors. In light of specific features and diverse applications of WSN, common assumptions from communication systems may not hold true and efficient application-specific protocols can be formulated. In this paper, we demonstrate this based on an interesting observation related to shortened Reed-Solomon (RS) codes for packet reliability in WSN. We show that multiple instances (γ) of RS codes defined on a smaller alphabet combined with interleaving result in smaller resource usage while the performance exceeds the benefits of a shortened RS code defined over a larger alphabet. In particular, the proposed scheme can have an error correction capability of up to γ times larger that for the conventional RS scheme without changing the rate of the code with much lower power, timing and memory requirements. Implementation results on 25mm motes developed by Tyndall National Institute show that such a scheme is 43% more power efficient compared to RS scheme with same code rate. Besides, such an approach results in 44% faster computations and 53% reduction in memory required.
UR - https://www.scopus.com/pages/publications/49749087541
U2 - 10.1109/ECCTD.2007.4529692
DO - 10.1109/ECCTD.2007.4529692
M3 - Chapter
AN - SCOPUS:49749087541
SN - 1424413427
SN - 9781424413423
T3 - European Conference on Circuit Theory and Design 2007, ECCTD 2007
SP - 699
EP - 702
BT - European Conference on Circuit Theory and Design 2007, ECCTD 2007
PB - IEEE Computer Society
T2 - European Conference on Circuit Theory and Design 2007, ECCTD 2007
Y2 - 26 August 2007 through 30 August 2007
ER -