Low energy ASIC elliptic curve processor

Elliptic curve cryptography is highly suited for implementation in resource constrained environments, however, dedicated hardware accelerators are necessary to provide the low power/energy security required in small, battery powered devices. This paper presents a low energy ASIC implementation of a characteristic 2 elliptic curve processor which consumes minimal energy per point multiplication, thereby prolonging battery life in constrained devices. Energy consumption is minimised by using low power design techniques in conjunction with an efficient, low area architecture in order to reduce the power consumption while maintaining a low number of clock cycles per operation. The energy/power/area trade-off is explored. In 0.13 μm CMOS technology the architecture consumes a minimum of 1.32 μJ at 500 kHz using a digit size of 15 and 24.6 kgates. The best area/energy trade off was 1.43 μJ at 500 kHz using a digit size of 11 and 22.3 kgates.