TY - GEN
T1 - Material characterisation and process development for miniaturised wireless sensor network module
AU - Majeed, Bivragh
AU - Van Jans, Jean Baptiste Sinte
AU - Paul, Indrajit
AU - Barton, John
AU - Mathuna, Sean C.O.
AU - Delaney, Kieran
PY - 2005
Y1 - 2005
N2 - The paper describes the work done in materials characterisation and process development of a proof-of-concept test vehicle for miniaturised wireless sensor network nodes. The test vehicle consists of thin silicon on a flexible substrate packaged in a novel 3-D structure. Two flexible substrates (commercial and in-house polyimide substrates, in the thickness range 25 microns down to 3 microns (each with 4 microns of sputtered copper) were analysed. It was observed that as the thickness of the polyimide substrate decreased below 9 microns, wrinkling became a major issue. The wrinkling was attributed to the copper sputtering. There was no adverse effect on test chip properties due to reduction in chip thickness while mechanically the chip was able to flex more with decreasing thickness and thus accommodate higher stresses. A finite element analysis model was constructed to observe the stress in silicon die under different loading conditions. The model matched well with the experimental values and showed that gold stud bumps cause stress in the chip. Test chips were packaged to develop a highly miniaturised 3D module by folding flexibly in an S shape structure. The 3D module consists of four test chips each having thickness of 50 microns, resulting in a packaged test device 450 microns in thickness and with a footprint of 18×7mm2. This module is being currently investigated for its implementation in a wireless sensor network system.
AB - The paper describes the work done in materials characterisation and process development of a proof-of-concept test vehicle for miniaturised wireless sensor network nodes. The test vehicle consists of thin silicon on a flexible substrate packaged in a novel 3-D structure. Two flexible substrates (commercial and in-house polyimide substrates, in the thickness range 25 microns down to 3 microns (each with 4 microns of sputtered copper) were analysed. It was observed that as the thickness of the polyimide substrate decreased below 9 microns, wrinkling became a major issue. The wrinkling was attributed to the copper sputtering. There was no adverse effect on test chip properties due to reduction in chip thickness while mechanically the chip was able to flex more with decreasing thickness and thus accommodate higher stresses. A finite element analysis model was constructed to observe the stress in silicon die under different loading conditions. The model matched well with the experimental values and showed that gold stud bumps cause stress in the chip. Test chips were packaged to develop a highly miniaturised 3D module by folding flexibly in an S shape structure. The 3D module consists of four test chips each having thickness of 50 microns, resulting in a packaged test device 450 microns in thickness and with a footprint of 18×7mm2. This module is being currently investigated for its implementation in a wireless sensor network system.
UR - https://www.scopus.com/pages/publications/33750372516
U2 - 10.1109/RME.2005.1543047
DO - 10.1109/RME.2005.1543047
M3 - Conference proceeding
AN - SCOPUS:33750372516
SN - 0780393457
SN - 9780780393455
T3 - 2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference
SP - 211
EP - 214
BT - 2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference
T2 - 2005 PhD Research in Microelectronics and Electronics Conference
Y2 - 25 July 2005 through 28 July 2005
ER -