@inproceedings{c88ca500f2bb46ba982f715f43672fcc,
title = "Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources",
abstract = "This paper proposes a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL) is used as the clock source. MATLAB Simulink models are used to create a time domain DPLL model with accurate Phase Noise. Time-to-digital converter (TDC) of the locked DPLL provides an estimate of jitter which is used with an analog differentiator to provide an estimate of the ADC sampling error. An improved compensation allows the ADC effective number of bits at high frequency to be improved from 2 bits to 6 bits.",
keywords = "ADC, compensation, Digital PLL, jitter, sampling",
author = "Hao Zheng and Eric Thompson and John Hogan and Daniel O'Hare",
note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 19th IEEE International New Circuits and Systems Conference, NEWCAS 2021 ; Conference date: 13-06-2021 Through 16-06-2021",
year = "2021",
month = jun,
day = "13",
doi = "10.1109/NEWCAS50681.2021.9462737",
language = "English",
series = "2021 19th IEEE International New Circuits and Systems Conference, NEWCAS 2021",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 19th IEEE International New Circuits and Systems Conference, NEWCAS 2021",
address = "United States",
}