TY - GEN
T1 - Modeling Degradation and Breakdown in SiO2 and High-k Gate Dielectrics
AU - Padovani, Andrea
AU - Torraca, Paolo La
AU - Larcher, Luca
AU - Strand, Jack
AU - Shluger, Alexander
N1 - Publisher Copyright:
© 2023 The Japan Society of Applied Physics.
PY - 2023
Y1 - 2023
N2 - We present a multiscale device simulation framework for modeling degradation and breakdown (BD) of gate dielectric stacks. It relies on an accurate, material-dependent description of the most relevant defect-related phenomena in dielectrics (charge trapping and transport, atomic species generation), and self-consistently models all degradation phases within the same physics-based description: stress-induced leakage current (SILC), soft (SBD), progressive (PBD) and hard breakdown (HBD). This methodology is applied to understand several key aspects related to the reliability of SiO2 and high-k (HK) gate dielectrics: i) characterization and role of defects responsible for the charge transport in fresh and stressed devices (SILC); ii) the differences observed in the SILC behavior of nMOS and pMOS transistors; iii) the degradation of bilayer SiOx/HfO2 stacks; and iv) the voltage dependence of the time-dependent dielectric breakdown (TDDB) distribution.
AB - We present a multiscale device simulation framework for modeling degradation and breakdown (BD) of gate dielectric stacks. It relies on an accurate, material-dependent description of the most relevant defect-related phenomena in dielectrics (charge trapping and transport, atomic species generation), and self-consistently models all degradation phases within the same physics-based description: stress-induced leakage current (SILC), soft (SBD), progressive (PBD) and hard breakdown (HBD). This methodology is applied to understand several key aspects related to the reliability of SiO2 and high-k (HK) gate dielectrics: i) characterization and role of defects responsible for the charge transport in fresh and stressed devices (SILC); ii) the differences observed in the SILC behavior of nMOS and pMOS transistors; iii) the degradation of bilayer SiOx/HfO2 stacks; and iv) the voltage dependence of the time-dependent dielectric breakdown (TDDB) distribution.
KW - dielectric breakdown
KW - Dielectric degradation
KW - Ginestra®
KW - stress-induced leakage currents (SILC)
KW - TDDB
UR - https://www.scopus.com/pages/publications/85179132545
U2 - 10.23919/SISPAD57422.2023.10319608
DO - 10.23919/SISPAD57422.2023.10319608
M3 - Conference proceeding
AN - SCOPUS:85179132545
T3 - International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
SP - 93
EP - 96
BT - 2023 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2023
Y2 - 27 September 2023 through 29 September 2023
ER -