Modeling Degradation and Breakdown in SiO2 and High-k Gate Dielectrics

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

We present a multiscale device simulation framework for modeling degradation and breakdown (BD) of gate dielectric stacks. It relies on an accurate, material-dependent description of the most relevant defect-related phenomena in dielectrics (charge trapping and transport, atomic species generation), and self-consistently models all degradation phases within the same physics-based description: stress-induced leakage current (SILC), soft (SBD), progressive (PBD) and hard breakdown (HBD). This methodology is applied to understand several key aspects related to the reliability of SiO2 and high-k (HK) gate dielectrics: i) characterization and role of defects responsible for the charge transport in fresh and stressed devices (SILC); ii) the differences observed in the SILC behavior of nMOS and pMOS transistors; iii) the degradation of bilayer SiOx/HfO2 stacks; and iv) the voltage dependence of the time-dependent dielectric breakdown (TDDB) distribution.

Original languageEnglish
Title of host publication2023 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages93-96
Number of pages4
ISBN (Electronic)9784863488038
DOIs
Publication statusPublished - 2023
Externally publishedYes
Event2023 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2023 - Kobe, Japan
Duration: 27 Sep 202329 Sep 2023

Publication series

NameInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Conference

Conference2023 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2023
Country/TerritoryJapan
CityKobe
Period27/09/2329/09/23

Keywords

  • dielectric breakdown
  • Dielectric degradation
  • Ginestra®
  • stress-induced leakage currents (SILC)
  • TDDB

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