Modelling of lateral bipolar devices in a CMOS process

In spite of the emergence of CMOS technology, the well-controlled characteristics of bipolar transistors retain many advantages over those of CMOS transistors for some critical analog applications. This is the reason why special technologies have been proposed to combine both types of transistors on the same chip [1], [2]. An inexpensive and widely applicable approach lies in using bipolars that are realizable with existing CMOS technologies. Bipolar transistors occur as parasitic devices in CMOS and it is not necessary to use additional processing steps in their manufacture. These bipolar transistors, therefore, provide cost effective devices which are relatively simple to fabricate. The extraction of a DC parameter set for the lateral device is more complicated than for a vertical device because of the presence of two parasitic vertical bipolar transistors which are formed by the emitter/collector, the base and the substrate regions. This paper proposes a method which involves the use of subcircuits incorporating three SPICE Gummel-Poon implementation models. The development of this model, its implementation and the results obtained will be outlined and discussed.