Modelling PWM Tones in Closed Loop Oscillator Based ADCs

This work proposes a method for modeling nonlinearity in amplifier-less VCO-based delta-sigma ADCs. The architecture presented in [1] is a promising candidate for implementing higher-order delta-sigma ADCs, comprising a ring oscillator, phase-frequency detector (PFD), integrating time-todigital converter (TDC), counter, difference unit, and feedback DAC. However, a drawback of this architecture is that the PFD introduces PWM tones, which are folded in-band by the sampling TDC. Modeling tools such as MATLAB/Simulink are widely used in delta-sigma ADC design. However, these models are inherently linear. This work proposes a methodology for modeling PWM tones, enabling ADC designs to be optimized systematically rather than through trial and error, thereby ensuring that in-band PWM tones are minimized. A modeling approach is introduced, and a model based on this method is developed. The model's output is compared to simulation results of a secondorder CCO-based delta-sigma ADC. Design trade-offs based on the model are discussed, demonstrating its potential to reduce design time for higher-order VCO-based delta-sigma ADCs.