Abstract
This letter describes a digital pulsewidth modulator that enables the generation of a large, adjustable number of pulsewidth modulated (PWM) outputs of programmable duty cycle and dead time, yet requiring just a small, fixed architecture. The design achieves a resolution of 255 ps using a composite PWM strategy that also minimizes clock frequency and area. It provides a practical solution to the problem of efficiently generating multiple high-resolution gate-drive signals and is particularly suited to the next generation of synchronously switched multiphase voltage regulator modules.
| Original language | English |
|---|---|
| Pages (from-to) | 842-846 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Power Electronics |
| Volume | 21 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - May 2006 |
Keywords
- Dc-dc power conversion
- Digital control
- Field-programmable gate arrays (FPGA)
- Switched-mode power supplies
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