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Nanowire to single-electron transistor transition in trigate SOI MOSFETs

  • Nima Dehdashti Akhavan
  • , Aryan Afzalian
  • , Chi Woo Lee
  • , Ran Yan
  • , Isabelle Ferain
  • , Pedram Razavi
  • , Ran Yu
  • , Giorgos Fagas
  • , Jean Pierre Colinge
  • Université catholique de Louvain

Research output: Contribution to journalArticlepeer-review

Abstract

We investigate the effect of symmetrical geometrical constrictions on the electrical characteristics of ultrathin silicon-on-insulator nanowires with a trigate structure using a 3-D numerical quantum simulator. Introducing barriers at the source and drain junctions profoundly alter the device physics and a transition from 1-D to 0-D quantum behavior is observed. The constrictions create resonance levels in the channel region of nanowire due to confinement in the three directions of space, which, in turn, causes oscillation of the I DVGS characteristic. Based on the observed characteristics, we derive a set of parameters that draws the line between 1-D and 0-D quantum behavior of silicon nanowire transistors.

Original languageEnglish
Article number5610985
Pages (from-to)26-32
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume58
Issue number1
DOIs
Publication statusPublished - Jan 2011

Keywords

  • 3-D device modeling
  • low temperature
  • low-dimensional structures
  • quantum transport
  • silicon nanowire transistor
  • tunnel-barrier field-effect transistor (FET)

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