Network-on-Chip interconnect for pairing-based cryptographic IP cores

On-chip data traffic in cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit power, congestion and scalability problems. In this paper, two case study cryptographic IP cores with demanding interconnect requirements are implemented on 65 nm CMOS. Lightweight, custom bus-replacement Networks-on-Chip (NoCs) have been developed for both cores. Results show that eliminating the 251-bit-wide cross-chip cryptographic buses dramatically improves the quality of physical implementation. The results have applicability to wire-constrained designs in other domains.