Optimisation of the SHA-2 family of hash functions on FPGAs

Robert P. McEvoy; Francis M. Crowe; Colin C. Murphy; William P. Marnane

doi:10.1109/ISVLSI.2006.70

Optimisation of the SHA-2 family of hash functions on FPGAs

Robert P. McEvoy
, Francis M. Crowe
, Colin C. Murphy
, William P. Marnane

University College Cork

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

Hash functions play an important role in modem cryptography. This paper investigates optimisation techniques that have recently been proposed in the literature. A new VLSI architecture for the SHA-256 and SHA-512 hash functions is presented, which combines two popular hardware optimisation techniques, namely pipelining and unrolling. The SHA processors are developed for implementation on FPGAs, thereby allowing rapid prototyping of several designs. Speed/area results from these processors are analysed and are shown to compare favourably with other FPGA-based implementations, achieving the fastest data throughputs in the literature to date.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Pages	317-322
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2006.70
Publication status	Published - 2006
Event	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 - Klarlsruhe, Germany Duration: 2 Mar 2006 → 3 Mar 2006

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Volume	2006

Conference

Conference	IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Country/Territory	Germany
City	Klarlsruhe
Period	2/03/06 → 3/03/06

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

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10.1109/ISVLSI.2006.70

Cite this

McEvoy, R. P., Crowe, F. M., Murphy, C. C., & Marnane, W. P. (2006). Optimisation of the SHA-2 family of hash functions on FPGAs. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 (pp. 317-322). Article 1602458 (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006; Vol. 2006). https://doi.org/10.1109/ISVLSI.2006.70

@inproceedings{cde653f48c774b098d2183abe91b4dd1,

title = "Optimisation of the SHA-2 family of hash functions on FPGAs",

abstract = "Hash functions play an important role in modem cryptography. This paper investigates optimisation techniques that have recently been proposed in the literature. A new VLSI architecture for the SHA-256 and SHA-512 hash functions is presented, which combines two popular hardware optimisation techniques, namely pipelining and unrolling. The SHA processors are developed for implementation on FPGAs, thereby allowing rapid prototyping of several designs. Speed/area results from these processors are analysed and are shown to compare favourably with other FPGA-based implementations, achieving the fastest data throughputs in the literature to date.",

author = "McEvoy, \{Robert P.\} and Crowe, \{Francis M.\} and Murphy, \{Colin C.\} and Marnane, \{William P.\}",

year = "2006",

doi = "10.1109/ISVLSI.2006.70",

language = "English",

isbn = "0769525334",

series = "Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006",

pages = "317--322",

booktitle = "Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006",

note = "IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 ; Conference date: 02-03-2006 Through 03-03-2006",

}

McEvoy, RP, Crowe, FM, Murphy, CC & Marnane, WP 2006, Optimisation of the SHA-2 family of hash functions on FPGAs. in Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006., 1602458, Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, vol. 2006, pp. 317-322, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, Klarlsruhe, Germany, 2/03/06. https://doi.org/10.1109/ISVLSI.2006.70

Optimisation of the SHA-2 family of hash functions on FPGAs. / McEvoy, Robert P.; Crowe, Francis M.; Murphy, Colin C. et al.
Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. 2006. p. 317-322 1602458 (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

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AB - Hash functions play an important role in modem cryptography. This paper investigates optimisation techniques that have recently been proposed in the literature. A new VLSI architecture for the SHA-256 and SHA-512 hash functions is presented, which combines two popular hardware optimisation techniques, namely pipelining and unrolling. The SHA processors are developed for implementation on FPGAs, thereby allowing rapid prototyping of several designs. Speed/area results from these processors are analysed and are shown to compare favourably with other FPGA-based implementations, achieving the fastest data throughputs in the literature to date.

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T3 - Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

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BT - Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

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McEvoy RP, Crowe FM, Murphy CC , Marnane WP. Optimisation of the SHA-2 family of hash functions on FPGAs. In Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006. 2006. p. 317-322. 1602458. (Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006). doi: 10.1109/ISVLSI.2006.70

Optimisation of the SHA-2 family of hash functions on FPGAs

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