Optimized polysilicon CMOS technology for gate array applications

Elena Manea; C. Gingu; Ileana Cernica; Fl Craciunoiu; S. Dunare; Ralu Divan; Camelia Dunare; Iulia Beldiman; M. Modreanu; D. Dascalu

Optimized polysilicon CMOS technology for gate array applications

Elena Manea
, C. Gingu
, Ileana Cernica
, Fl Craciunoiu
, S. Dunare
, Ralu Divan
, Camelia Dunare
, Iulia Beldiman
, M. Modreanu
, D. Dascalu

National Institute for Research and Development in Microtechnologies Romania

Research output: Contribution to conference › Paper › peer-review

Abstract

The gate arrays option in manufacturing ASIC CMOS is conditioned by the possibility of satisfying small orders requirements of small- and medium-sized electronic equipment manufacturing companies, in a large variety of circuits. The authors present contributions in optimizing critical processes for an n-well CMOS polysilicon gate arrays technology. Technological achievements were proved by measurements on the test devices but mainly by array chip fabrication. There were manufactured chips for specialized circuits intended for telephone switching equipment.

Original language	English
Pages	333-336
Number of pages	4
Publication status	Published - 1998
Externally published	Yes
Event	Proceedings of the 1998 International Semiconductor Conference, CAS'98. Part 2 (of 2) - Sinaia, Romania Duration: 6 Oct 1998 → 10 Oct 1998

Conference

Conference	Proceedings of the 1998 International Semiconductor Conference, CAS'98. Part 2 (of 2)
City	Sinaia, Romania
Period	6/10/98 → 10/10/98

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

Cite this

@conference{69fb71b6c96e423286006db526284e12,

title = "Optimized polysilicon CMOS technology for gate array applications",

abstract = "The gate arrays option in manufacturing ASIC CMOS is conditioned by the possibility of satisfying small orders requirements of small- and medium-sized electronic equipment manufacturing companies, in a large variety of circuits. The authors present contributions in optimizing critical processes for an n-well CMOS polysilicon gate arrays technology. Technological achievements were proved by measurements on the test devices but mainly by array chip fabrication. There were manufactured chips for specialized circuits intended for telephone switching equipment.",

author = "Elena Manea and C. Gingu and Ileana Cernica and Fl Craciunoiu and S. Dunare and Ralu Divan and Camelia Dunare and Iulia Beldiman and M. Modreanu and D. Dascalu",

year = "1998",

language = "English",

pages = "333--336",

note = "Proceedings of the 1998 International Semiconductor Conference, CAS'98. Part 2 (of 2) ; Conference date: 06-10-1998 Through 10-10-1998",

}

TY - CONF

T1 - Optimized polysilicon CMOS technology for gate array applications

AU - Manea, Elena

AU - Gingu, C.

AU - Cernica, Ileana

AU - Craciunoiu, Fl

AU - Dunare, S.

AU - Divan, Ralu

AU - Dunare, Camelia

AU - Beldiman, Iulia

AU - Modreanu, M.

AU - Dascalu, D.

PY - 1998

Y1 - 1998

N2 - The gate arrays option in manufacturing ASIC CMOS is conditioned by the possibility of satisfying small orders requirements of small- and medium-sized electronic equipment manufacturing companies, in a large variety of circuits. The authors present contributions in optimizing critical processes for an n-well CMOS polysilicon gate arrays technology. Technological achievements were proved by measurements on the test devices but mainly by array chip fabrication. There were manufactured chips for specialized circuits intended for telephone switching equipment.

AB - The gate arrays option in manufacturing ASIC CMOS is conditioned by the possibility of satisfying small orders requirements of small- and medium-sized electronic equipment manufacturing companies, in a large variety of circuits. The authors present contributions in optimizing critical processes for an n-well CMOS polysilicon gate arrays technology. Technological achievements were proved by measurements on the test devices but mainly by array chip fabrication. There were manufactured chips for specialized circuits intended for telephone switching equipment.

UR - https://www.scopus.com/pages/publications/0032314867

M3 - Paper

AN - SCOPUS:0032314867

SP - 333

EP - 336

T2 - Proceedings of the 1998 International Semiconductor Conference, CAS'98. Part 2 (of 2)

Y2 - 6 October 1998 through 10 October 1998

ER -

Optimized polysilicon CMOS technology for gate array applications

Abstract

Conference

UN SDGs

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