Optimizing designs for hardware compilation to FPGAs

F. J. O'Reilly; W. P. Marnane; P. J. Murphy

Optimizing designs for hardware compilation to FPGAs

F. J. O'Reilly
, W. P. Marnane
, P. J. Murphy

University College Cork

Research output: Contribution to conference › Paper › peer-review

Abstract

Field Programmable Gate Arrays with their re-configurable architectures are a powerful tool for implementing Re-configurable Computing. Using the facility of reprogrammability, designs can be optimized for specific cases and then implemented in hardware, achieving performance improvements over the all software design. As the physical architecture itself places size and speed constraints on the designs, we present bit level optimizations and a design and layout tool to improve the benefits achievable with the reprogrammability, for regular numerical designs.

Original language	English
Pages	522-531
Number of pages	10
Publication status	Published - 1997
Event	Proceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation - Leicester, UK Duration: 3 Nov 1997 → 5 Nov 1997

Conference

Conference	Proceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation
City	Leicester, UK
Period	3/11/97 → 5/11/97

Cite this

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title = "Optimizing designs for hardware compilation to FPGAs",

abstract = "Field Programmable Gate Arrays with their re-configurable architectures are a powerful tool for implementing Re-configurable Computing. Using the facility of reprogrammability, designs can be optimized for specific cases and then implemented in hardware, achieving performance improvements over the all software design. As the physical architecture itself places size and speed constraints on the designs, we present bit level optimizations and a design and layout tool to improve the benefits achievable with the reprogrammability, for regular numerical designs.",

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year = "1997",

language = "English",

pages = "522--531",

note = "Proceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation ; Conference date: 03-11-1997 Through 05-11-1997",

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TY - CONF

T1 - Optimizing designs for hardware compilation to FPGAs

AU - O'Reilly, F. J.

AU - Marnane, W. P.

AU - Murphy, P. J.

PY - 1997

Y1 - 1997

N2 - Field Programmable Gate Arrays with their re-configurable architectures are a powerful tool for implementing Re-configurable Computing. Using the facility of reprogrammability, designs can be optimized for specific cases and then implemented in hardware, achieving performance improvements over the all software design. As the physical architecture itself places size and speed constraints on the designs, we present bit level optimizations and a design and layout tool to improve the benefits achievable with the reprogrammability, for regular numerical designs.

AB - Field Programmable Gate Arrays with their re-configurable architectures are a powerful tool for implementing Re-configurable Computing. Using the facility of reprogrammability, designs can be optimized for specific cases and then implemented in hardware, achieving performance improvements over the all software design. As the physical architecture itself places size and speed constraints on the designs, we present bit level optimizations and a design and layout tool to improve the benefits achievable with the reprogrammability, for regular numerical designs.

UR - https://www.scopus.com/pages/publications/0031347377

M3 - Paper

AN - SCOPUS:0031347377

SP - 522

EP - 531

T2 - Proceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation

Y2 - 3 November 1997 through 5 November 1997

ER -

Optimizing designs for hardware compilation to FPGAs

Abstract

Conference

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