Power analysis of sorting algorithms on FPGA using OpenCL

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

With the advent of big data and cloud computing, there is tremendous interest in optimised algorithms and architectures for sorting either using software or hardware. Field Programmable Gate Arrays(FPGAS) are being increasingly used in high end data servers providing a bridge between the flexibility of software and performance benefits of hardware. In this paper we look at implementations of some of the most popular sorting algorithms using OpenCL which take advantage of FPGA architecture. We evaluate these implementations in terms of power consumption which is measured using dedicated server power loggers and execution on Intel Arria 10 hardware. Our experiments show that taking advantage of software FIFOs have a significant impact on power consumption as well as requiring less hardware and memory resources.

Original languageEnglish
Title of host publication29th Irish Signals and Systems Conference, ISSC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538660461
DOIs
Publication statusPublished - 20 Dec 2018
Event29th Irish Signals and Systems Conference, ISSC 2018 - Belfast, United Kingdom
Duration: 21 Jun 201822 Jun 2018

Publication series

Name29th Irish Signals and Systems Conference, ISSC 2018

Conference

Conference29th Irish Signals and Systems Conference, ISSC 2018
Country/TerritoryUnited Kingdom
CityBelfast
Period21/06/1822/06/18

Keywords

  • Acceleration
  • Bitonic Sort
  • Energy efficiency
  • FPGAS
  • Insertion Sort
  • Odd/Even Sort
  • OpenCL
  • Power Consumption
  • Radix Sort
  • Sorting

Fingerprint

Dive into the research topics of 'Power analysis of sorting algorithms on FPGA using OpenCL'. Together they form a unique fingerprint.

Cite this