TY - GEN
T1 - Power and area efficient comb-based decimator for Sigma-Delta ADCs with high decimation factors
AU - Salgado, Gerardo Molina
AU - Dolecek, Gordana Jovanovic
AU - De La Rosa, Jose M.
PY - 2013
Y1 - 2013
N2 - This paper introduces a power and area efficient comb-based decimation structure, particularly suited for high values of decimation factors which are a power of two. The proposed topology has two stages, where the first stage is in a non-recursive form and the second one is in a recursive form (CIC filter). Moreover, a slight modification of the proposed decimator structure is presented in order to obtain an improved alias rejection. Simulation results are shown to validate the proposed approach.
AB - This paper introduces a power and area efficient comb-based decimation structure, particularly suited for high values of decimation factors which are a power of two. The proposed topology has two stages, where the first stage is in a non-recursive form and the second one is in a recursive form (CIC filter). Moreover, a slight modification of the proposed decimator structure is presented in order to obtain an improved alias rejection. Simulation results are shown to validate the proposed approach.
UR - https://www.scopus.com/pages/publications/84883416485
U2 - 10.1109/ISCAS.2013.6572082
DO - 10.1109/ISCAS.2013.6572082
M3 - Conference proceeding
AN - SCOPUS:84883416485
SN - 9781467357609
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1260
EP - 1263
BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Y2 - 19 May 2013 through 23 May 2013
ER -