Pre-layout decoupling capacitance estimation and allocation for noise-aware crypto-system on chip applications

Estimation of decoupling capacitance allocation for noise suppression at pre layout level is the objective of our paper. The experiment is based on the module wise estimation of voltage drop and decoupling capacitance placement. Present trends in VLSI design are inclined towards system on chip (SoC) design. Hence, efficient design plans and CAD approaches should be developed in the SoC domain. We investigate multi-core circuits in our work and consider the custom crypto-cores as example circuits, because they are well used as hardware accelerators in many of the present day application circuits. The novelty in our work lies in the fact that by using our approaches noise can be reduced by 87.23% in an average at the pre-layout stage.