Predictable, low-power arithmetic logic unit for the 8051 microcontroller using asynchronous logic

Modern embedded systems require all their components, including their microcontroller, to be optimised with respect to the power budget. Two properties are desirable. The first is low power usage and the second is predicable power usage, for improved estimation of firmware performance. In this paper we present all the arithmetic circuits for an ALU of an 8051 microcontroller implemented in Asynchronous Charge Sharing Logic (ACSL). This implementation seeks to give these two desirable properties for a processor for embedded systems. The first, low power usage, obtained through charge sharing. The second, predictable power usage, is sought by ensuring that the power required to complete an operation is independent of its inputs. The experimental techniques used in designing ACSL were also improved in the execution of this work, allowing the ACSL circuits to be entered using Verilog for fast initial testing and then translated to SPICE for detailed simulation. Through implementation and simulation, it was determined that the use of ACSL can offer power predictability.