TY - CHAP
T1 - Prototyping a bidirectional processor design based on reversible principles
AU - Vasudevan, Dilip
AU - Schellekens, Michel
AU - Zeinolabedini, Nasim
AU - Popovici, Emanuel
PY - 2011
Y1 - 2011
N2 - This work is motivated towards building a complete bidirectional architecture based on the reversible principles and to study the feasibility of implementation and bottlenecks encountered during this design. A new bidirectional architecture with each core built using infamous single cycle MIPS architecture is proposed. The bidirectional design facilitates the reversible principle of forward and reverse direction of execution of the architecture. The main goal of this work is to implement and empirically study the outcomes of the reversible system built. The architecture is implemented using commercially available 90 nm technology node. The processor operates at 200 MHz with medium mapping and optimization effort and the performance can be improved with further optimization.
AB - This work is motivated towards building a complete bidirectional architecture based on the reversible principles and to study the feasibility of implementation and bottlenecks encountered during this design. A new bidirectional architecture with each core built using infamous single cycle MIPS architecture is proposed. The bidirectional design facilitates the reversible principle of forward and reverse direction of execution of the architecture. The main goal of this work is to implement and empirically study the outcomes of the reversible system built. The architecture is implemented using commercially available 90 nm technology node. The processor operates at 200 MHz with medium mapping and optimization effort and the performance can be improved with further optimization.
KW - Bidirectional Processor Design
KW - MIPS
KW - Reversible Computing
UR - https://www.scopus.com/pages/publications/84856748507
U2 - 10.1109/ISICir.2011.6131962
DO - 10.1109/ISICir.2011.6131962
M3 - Chapter
AN - SCOPUS:84856748507
SN - 9781612848648
T3 - 2011 International Symposium on Integrated Circuits, ISIC 2011
SP - 325
EP - 328
BT - 2011 International Symposium on Integrated Circuits, ISIC 2011
T2 - 2011 International Symposium on Integrated Circuits, ISIC 2011
Y2 - 12 December 2011 through 14 December 2011
ER -