Quantitative prediction of junction leakage in bulk-technology CMOS devices

Junction leakage becomes more significant as metal-oxide-semiconductor (MOS) technologies scale down in bulk-silicon. In this work we quantify the four key elements to junction leakage generation through a combination of experiment and device simulation. These elements are: (i) ultra-shallow junction steepness, (ii) channel and pocket concentrations, (iii) junction curvature, and (iv) the presence of residual defects. We first characterize n⁺/p and p⁺/n diodes to quantify how changes in doping profiles affect reverse bias leakage. Diodes with end-of-range (EOR) silicon defects intentionally located in the junction depletion region are also characterized to quantify their contribution. This feeds into a device simulation study to gain insight in the experimental results and in the capabilities of available physical models. Thereafter simulation is used to predict leakage in future generation bulk-silicon MOS devices. In summary, band-to-band tunneling (BBT) due to aggressively scaled doping profiles and trap-assisted tunneling (TAT) due to the increased presence of defects make off-state low-standby-power leakage targets difficult to meet. With the increase of junction leakage from aggressively scaled ultra-shallow junctions, the assumption that the subthreshold leakage component dominates off-state current is no longer valid.