Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder

This paper describes an FPGA implementation of a decoder for a particular family of low density parity check (LDPC) codes, the quasi-cyclic LDPC codes. The structure of a quasi-cyclic code is well known and allows us to reduce the complexity of the interconnections between bit nodes and check nodes. The decoder has a semi-parallel architecture and it takes full advantage of the structure of the code and the hardware resources present in an FPGA. We achieve simple memory controller resulting in an efficient use of the memory. The decoder is implemented based on the parameters that characterize a quasi-cyclic LDPC code. This makes it easily adaptable for a class of quasi-cyclic codes. We evaluate the performance of our codes and present some FPGA design trade-off.