Reducing routing congestion in a cryptographic IP core using NoC interconnect

T. English; E. Popovici; M. Keller; W. P. Marnane

doi:10.1049/cp.2010.0514

Reducing routing congestion in a cryptographic IP core using NoC interconnect

T. English
, E. Popovici
, M. Keller
, W. P. Marnane

University College Cork

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

On-chip data traffic in coding and cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit congestion, power and scalability problems. In this paper, we report on a case study IP core for Identity-based Encryption which has been implemented in 65nm CMOS. Problematic wide buses are replaced by a simple circuit-switched NoC-style interconnect. Congestion is reduced dramatically, allowing higher utilisation and resulting in lower switching power and better reliability. The results have applicability to wire-constrained designs in other domains.

Original language	English
Title of host publication	IET Irish Signals and Systems Conference, ISSC 2010
Pages	210-215
Number of pages	6
Edition	566 CP
DOIs	https://doi.org/10.1049/cp.2010.0514
Publication status	Published - 2010
Event	IET Irish Signals and Systems Conference, ISSC 2010 - Cork, Ireland Duration: 23 Jun 2010 → 24 Jun 2010

Publication series

Name	IET Conference Publications
Number	566 CP
Volume	2010

Conference

Conference	IET Irish Signals and Systems Conference, ISSC 2010
Country/Territory	Ireland
City	Cork
Period	23/06/10 → 24/06/10

Keywords

Circuit-switched
Cryptography
Interconnect
Network-on-Chip
Tate Pairing

Access to Document

10.1049/cp.2010.0514

Cite this

@inproceedings{f31afb653bc94bbdbd0157a3b14d639c,

title = "Reducing routing congestion in a cryptographic IP core using NoC interconnect",

abstract = "On-chip data traffic in coding and cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit congestion, power and scalability problems. In this paper, we report on a case study IP core for Identity-based Encryption which has been implemented in 65nm CMOS. Problematic wide buses are replaced by a simple circuit-switched NoC-style interconnect. Congestion is reduced dramatically, allowing higher utilisation and resulting in lower switching power and better reliability. The results have applicability to wire-constrained designs in other domains.",

keywords = "Circuit-switched, Cryptography, Interconnect, Network-on-Chip, Tate Pairing",

author = "T. English and E. Popovici and M. Keller and Marnane, \{W. P.\}",

year = "2010",

doi = "10.1049/cp.2010.0514",

language = "English",

isbn = "9781849192521",

series = "IET Conference Publications",

number = "566 CP",

pages = "210--215",

booktitle = "IET Irish Signals and Systems Conference, ISSC 2010",

edition = "566 CP",

note = "IET Irish Signals and Systems Conference, ISSC 2010 ; Conference date: 23-06-2010 Through 24-06-2010",

}

English, T, Popovici, E, Keller, M & Marnane, WP 2010, Reducing routing congestion in a cryptographic IP core using NoC interconnect. in IET Irish Signals and Systems Conference, ISSC 2010. 566 CP edn, IET Conference Publications, no. 566 CP, vol. 2010, pp. 210-215, IET Irish Signals and Systems Conference, ISSC 2010, Cork, Ireland, 23/06/10. https://doi.org/10.1049/cp.2010.0514

TY - GEN

T1 - Reducing routing congestion in a cryptographic IP core using NoC interconnect

AU - English, T.

AU - Popovici, E.

AU - Keller, M.

AU - Marnane, W. P.

PY - 2010

Y1 - 2010

N2 - On-chip data traffic in coding and cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit congestion, power and scalability problems. In this paper, we report on a case study IP core for Identity-based Encryption which has been implemented in 65nm CMOS. Problematic wide buses are replaced by a simple circuit-switched NoC-style interconnect. Congestion is reduced dramatically, allowing higher utilisation and resulting in lower switching power and better reliability. The results have applicability to wire-constrained designs in other domains.

AB - On-chip data traffic in coding and cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit congestion, power and scalability problems. In this paper, we report on a case study IP core for Identity-based Encryption which has been implemented in 65nm CMOS. Problematic wide buses are replaced by a simple circuit-switched NoC-style interconnect. Congestion is reduced dramatically, allowing higher utilisation and resulting in lower switching power and better reliability. The results have applicability to wire-constrained designs in other domains.

KW - Circuit-switched

KW - Cryptography

KW - Interconnect

KW - Network-on-Chip

KW - Tate Pairing

UR - https://www.scopus.com/pages/publications/78649609653

U2 - 10.1049/cp.2010.0514

DO - 10.1049/cp.2010.0514

M3 - Conference proceeding

AN - SCOPUS:78649609653

SN - 9781849192521

T3 - IET Conference Publications

SP - 210

EP - 215

BT - IET Irish Signals and Systems Conference, ISSC 2010

T2 - IET Irish Signals and Systems Conference, ISSC 2010

Y2 - 23 June 2010 through 24 June 2010

ER -

Reducing routing congestion in a cryptographic IP core using NoC interconnect

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Keywords

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