Reed-Solomon codecs for optical communications

This paper presents methods for improving the performance of a Reed-Solomon codec (encoder/decoder) so that it matches the requirements of high throughput/low power of an optical communication system. It is shown that by a careful selection of the underlying Galois field arithmetic architectures, and of the algorithms for finding the error locations and error values, the performance can be improved substantially over current techniques. We show that the symbol-parallel Fitzpatrick algorithm for solving the key equation uses 30% fewer multipliers than Berlekamp-Massey type architectures, thus achieving a cost reduction for the entire codec. The implementations are synthesised for Xilinx FPGAs and LSI lca 300 k array-of-gates technologies.