Reliability driven mixed critical tasks processing on FPGAs against hardware trojan attacks

The property of dynamic partial reconfiguration of modern field programmable gate arrays (FPGAs) has made it feasible to execute various mixed critical tasks on the same platform. This requires partitioning the FPGA fabric into several virtual portions (VPs) and a scheduling methodology to determine which task is to be executed when and in which FPGA VP. Executing a task in an FPGA VP requires runtime configuring of the VP with a bitstream or a reconfigurable intellectual property, procured from a third party intellectual property (3PIP) vendor. Recent literature has exposed the presence of malicious elements like hardware trojan horses (HTHs) in such 3PIP bitstreams. Such HTH is particularly dangerous as these remain dormant during testing and initial stages of operation, but gets activated suddenly at runtime to jeopardize the basic security primitives of the system. Thus, reliability driven mixed critical tasks processing on FPGAs against HTH attacks is important. Firstly, reliability driven mixed critical periodic task schedule generation against HTH attacks is focused. Secondly, reliability ensured execution of mixed critical aperiodic and sporadic tasks in the generated periodic task schedule is considered. Experimentation is carried out with a variety of bitstreams and performance evaluation is performed via metrics like task success rate, task rejection rate and task preemption rate.