Role of interface and bulk traps on the capacitance–voltage characteristics of WS₂/Al₂O₃/Si capacitors

This paper reports the capacitance–voltage (CV) characteristics of 2D material based vertical semiconductor-oxide semiconductor (SOS) capacitors (CAPs) at different ac frequencies. The SOS structure is made of mechanically exfoliated WS₂ flakes, deposited on a p-type silicon substrate covered by Al₂O₃ dielectric layer. The device exhibits n-type behavior as WS₂ goes into accumulation at positive biases on the p-Si, with a non-intentional doping concentration of around 10¹⁷cm^-3. By double sweeping the DC bias, a hysteresis cycle occurs in the CV response. On the other hand, a low frequency dispersion is observed in the depletion mode implying a low WS₂/Al₂O₃ interface trap density. Our quantitative analysis confirms a low interface trap density of D_it∼10¹¹cm^-2eV^-1. We also report our observation on a distortion in the CV characteristics, observed as the depletion width expands into the WS₂ at negative voltage bias. This feature does not depend on the ac signal frequency. Based on our CV analysis, we have proposed a hypothesis with a schematic band-energy model where the CV distortion is attributed to localized bulk traps in the WS₂ located within the first few nm from the WS₂/Al₂O₃ interface.