Scalability of InGaAs gate-All-Around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm

X. Zhou; N. Waldron; G. Boccardi; F. Sebaai; C. Merckling; G. Eneman; S. Sioncke; L. Nyns; A. Opdebeeck; J. W. Maes; Q. Xie; M. Givens; F. Tang; X. Jiang; W. Guo; B. Kunert; L. Teugels; K. Devriendt; A. Sibaja Hernandez; J. Franco; D. Van Dorp; K. Barla; N. Collaert; A. V.Y. Thean

doi:10.1109/VLSIT.2016.7573420

Scalability of InGaAs gate-All-Around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and L_g down to 36nm

X. Zhou
, N. Waldron
, G. Boccardi
, F. Sebaai
, C. Merckling
, G. Eneman
, S. Sioncke
, L. Nyns
, A. Opdebeeck
, J. W. Maes
, Q. Xie
, M. Givens
, F. Tang
, X. Jiang
, W. Guo
, B. Kunert
, L. Teugels
, K. Devriendt
, A. Sibaja Hernandez
, J. Franco

D. Van Dorp, K. Barla, N. Collaert, A. V.Y. Thean

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

We report In_0.53GaAs-channel gate-All-Around FETs with channel width down to 7nm and L_g down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g_m by 25% compared to InAs S/D. A g_m of 1310 μS/μm with an SS_sat of 82mV/dec is achieved for an L_g=46nm device. At this L_g, a record I_on above 200μA/μm is obtained at I_off of 100nA/μm and V_ds=0.5V on a 300mm Si platform.

Original language	English
Title of host publication	2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509006373
DOIs	https://doi.org/10.1109/VLSIT.2016.7573420
Publication status	Published - 21 Sep 2016
Externally published	Yes
Event	36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, United States Duration: 13 Jun 2016 → 16 Jun 2016

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2016-September
ISSN (Print)	0743-1562

Conference

Conference	36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
Country/Territory	United States
City	Honolulu
Period	13/06/16 → 16/06/16

Access to Document

10.1109/VLSIT.2016.7573420

Cite this

Zhou, X., Waldron, N., Boccardi, G., Sebaai, F., Merckling, C., Eneman, G., Sioncke, S., Nyns, L., Opdebeeck, A., Maes, J. W., Xie, Q., Givens, M., Tang, F., Jiang, X., Guo, W., Kunert, B., Teugels, L., Devriendt, K., Hernandez, A. S., ... Thean, A. V. Y. (2016). Scalability of InGaAs gate-All-Around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and L_g down to 36nm. In 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016 Article 7573420 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2016-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2016.7573420

Zhou, X. ; Waldron, N. ; Boccardi, G. et al. / Scalability of InGaAs gate-All-Around FET integrated on 300mm Si platform : Demonstration of channel width down to 7nm and L_g down to 36nm. 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{adbb8a0faa6a4ed18ee29a17ca22e32c,

title = "Scalability of InGaAs gate-All-Around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm",

abstract = "We report In0.53GaAs-channel gate-All-Around FETs with channel width down to 7nm and Lg down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak gm by 25\% compared to InAs S/D. A gm of 1310 μS/μm with an SSsat of 82mV/dec is achieved for an Lg=46nm device. At this Lg, a record Ion above 200μA/μm is obtained at Ioff of 100nA/μm and Vds=0.5V on a 300mm Si platform.",

author = "X. Zhou and N. Waldron and G. Boccardi and F. Sebaai and C. Merckling and G. Eneman and S. Sioncke and L. Nyns and A. Opdebeeck and Maes, \{J. W.\} and Q. Xie and M. Givens and F. Tang and X. Jiang and W. Guo and B. Kunert and L. Teugels and K. Devriendt and Hernandez, \{A. Sibaja\} and J. Franco and \{Van Dorp\}, D. and K. Barla and N. Collaert and Thean, \{A. V.Y.\}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 ; Conference date: 13-06-2016 Through 16-06-2016",

year = "2016",

month = sep,

day = "21",

doi = "10.1109/VLSIT.2016.7573420",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016",

address = "United States",

}

Zhou, X, Waldron, N, Boccardi, G, Sebaai, F, Merckling, C, Eneman, G, Sioncke, S, Nyns, L, Opdebeeck, A, Maes, JW, Xie, Q, Givens, M, Tang, F, Jiang, X, Guo, W, Kunert, B, Teugels, L, Devriendt, K, Hernandez, AS, Franco, J, Van Dorp, D, Barla, K, Collaert, N & Thean, AVY 2016, Scalability of InGaAs gate-All-Around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and L_g down to 36nm. in 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016., 7573420, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2016-September, Institute of Electrical and Electronics Engineers Inc., 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016, Honolulu, United States, 13/06/16. https://doi.org/10.1109/VLSIT.2016.7573420

Scalability of InGaAs gate-All-Around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and L_g down to 36nm. / Zhou, X.; Waldron, N.; Boccardi, G. et al.
2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7573420 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2016-September).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

TY - GEN

T1 - Scalability of InGaAs gate-All-Around FET integrated on 300mm Si platform

T2 - 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016

AU - Zhou, X.

AU - Waldron, N.

AU - Boccardi, G.

AU - Sebaai, F.

AU - Merckling, C.

AU - Eneman, G.

AU - Sioncke, S.

AU - Nyns, L.

AU - Opdebeeck, A.

AU - Maes, J. W.

AU - Xie, Q.

AU - Givens, M.

AU - Tang, F.

AU - Jiang, X.

AU - Guo, W.

AU - Kunert, B.

AU - Teugels, L.

AU - Devriendt, K.

AU - Hernandez, A. Sibaja

AU - Franco, J.

AU - Van Dorp, D.

AU - Barla, K.

AU - Collaert, N.

AU - Thean, A. V.Y.

PY - 2016/9/21

Y1 - 2016/9/21

N2 - We report In0.53GaAs-channel gate-All-Around FETs with channel width down to 7nm and Lg down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak gm by 25% compared to InAs S/D. A gm of 1310 μS/μm with an SSsat of 82mV/dec is achieved for an Lg=46nm device. At this Lg, a record Ion above 200μA/μm is obtained at Ioff of 100nA/μm and Vds=0.5V on a 300mm Si platform.

AB - We report In0.53GaAs-channel gate-All-Around FETs with channel width down to 7nm and Lg down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak gm by 25% compared to InAs S/D. A gm of 1310 μS/μm with an SSsat of 82mV/dec is achieved for an Lg=46nm device. At this Lg, a record Ion above 200μA/μm is obtained at Ioff of 100nA/μm and Vds=0.5V on a 300mm Si platform.

UR - https://www.scopus.com/pages/publications/84990954962

U2 - 10.1109/VLSIT.2016.7573420

DO - 10.1109/VLSIT.2016.7573420

M3 - Conference proceeding

AN - SCOPUS:84990954962

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 13 June 2016 through 16 June 2016

ER -

Zhou X, Waldron N, Boccardi G, Sebaai F, Merckling C, Eneman G et al. Scalability of InGaAs gate-All-Around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and L_g down to 36nm. In 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7573420. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2016.7573420