Scaling CMOS beyond Si FinFET: An analog/RF perspective

B. Parvais; G. Hellings; M. Simicic; P. Weckx; J. Mitard; D. Jang; V. Deshpande; B. Van Liempc; A. Veloso; A. Vandooren; N. Waldron; P. Wambacq; N. Collaert; D. Verkest

doi:10.1109/ESSDERC.2018.8486857

Scaling CMOS beyond Si FinFET: An analog/RF perspective

B. Parvais
, G. Hellings
, M. Simicic
, P. Weckx
, J. Mitard
, D. Jang
, V. Deshpande
, B. Van Liempc
, A. Veloso
, A. Vandooren
, N. Waldron
, P. Wambacq
, N. Collaert
, D. Verkest

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

FinFET has been introduced in the 22/16nm node to continue CMOS logic scaling. The very tight pitches foreseen for the coming generation necessitate the introduction of different scaling boosters. In this paper, we review how these elements affect the analog device performance. The benefits of alternative channel material for dedicated RF applications and the related integration challenges are also discussed.

Original language	English
Title of host publication	2018 48th European Solid-State Device Research Conference, ESSDERC 2018
Publisher	Editions Frontieres
Pages	158-161
Number of pages	4
ISBN (Electronic)	9781538654019
DOIs	https://doi.org/10.1109/ESSDERC.2018.8486857
Publication status	Published - 8 Oct 2018
Externally published	Yes
Event	48th European Solid-State Device Research Conference, ESSDERC 2018 - Dresden, Germany Duration: 3 Sep 2018 → 6 Sep 2018

Publication series

Name	European Solid-State Device Research Conference
Volume	2018-September
ISSN (Print)	1930-8876

Conference

Conference	48th European Solid-State Device Research Conference, ESSDERC 2018
Country/Territory	Germany
City	Dresden
Period	3/09/18 → 6/09/18

Access to Document

10.1109/ESSDERC.2018.8486857

Cite this

Parvais, B., Hellings, G., Simicic, M., Weckx, P., Mitard, J., Jang, D., Deshpande, V., Van Liempc, B., Veloso, A., Vandooren, A., Waldron, N., Wambacq, P., Collaert, N., & Verkest, D. (2018). Scaling CMOS beyond Si FinFET: An analog/RF perspective. In 2018 48th European Solid-State Device Research Conference, ESSDERC 2018 (pp. 158-161). Article 8486857 (European Solid-State Device Research Conference; Vol. 2018-September). Editions Frontieres. https://doi.org/10.1109/ESSDERC.2018.8486857

@inbook{dbbca44aae2a4b998587769bf3e76d51,

title = "Scaling CMOS beyond Si FinFET: An analog/RF perspective",

abstract = "FinFET has been introduced in the 22/16nm node to continue CMOS logic scaling. The very tight pitches foreseen for the coming generation necessitate the introduction of different scaling boosters. In this paper, we review how these elements affect the analog device performance. The benefits of alternative channel material for dedicated RF applications and the related integration challenges are also discussed.",

author = "B. Parvais and G. Hellings and M. Simicic and P. Weckx and J. Mitard and D. Jang and V. Deshpande and \{Van Liempc\}, B. and A. Veloso and A. Vandooren and N. Waldron and P. Wambacq and N. Collaert and D. Verkest",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 48th European Solid-State Device Research Conference, ESSDERC 2018 ; Conference date: 03-09-2018 Through 06-09-2018",

year = "2018",

month = oct,

day = "8",

doi = "10.1109/ESSDERC.2018.8486857",

language = "English",

series = "European Solid-State Device Research Conference",

publisher = "Editions Frontieres",

pages = "158--161",

booktitle = "2018 48th European Solid-State Device Research Conference, ESSDERC 2018",

address = "France",

}

Parvais, B, Hellings, G, Simicic, M, Weckx, P, Mitard, J, Jang, D, Deshpande, V, Van Liempc, B, Veloso, A, Vandooren, A, Waldron, N, Wambacq, P, Collaert, N & Verkest, D 2018, Scaling CMOS beyond Si FinFET: An analog/RF perspective. in 2018 48th European Solid-State Device Research Conference, ESSDERC 2018., 8486857, European Solid-State Device Research Conference, vol. 2018-September, Editions Frontieres, pp. 158-161, 48th European Solid-State Device Research Conference, ESSDERC 2018, Dresden, Germany, 3/09/18. https://doi.org/10.1109/ESSDERC.2018.8486857

Scaling CMOS beyond Si FinFET: An analog/RF perspective. / Parvais, B.; Hellings, G.; Simicic, M. et al.
2018 48th European Solid-State Device Research Conference, ESSDERC 2018. Editions Frontieres, 2018. p. 158-161 8486857 (European Solid-State Device Research Conference; Vol. 2018-September).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

TY - CHAP

T1 - Scaling CMOS beyond Si FinFET

T2 - 48th European Solid-State Device Research Conference, ESSDERC 2018

AU - Parvais, B.

AU - Hellings, G.

AU - Simicic, M.

AU - Weckx, P.

AU - Mitard, J.

AU - Jang, D.

AU - Deshpande, V.

AU - Van Liempc, B.

AU - Veloso, A.

AU - Vandooren, A.

AU - Waldron, N.

AU - Wambacq, P.

AU - Collaert, N.

AU - Verkest, D.

PY - 2018/10/8

Y1 - 2018/10/8

N2 - FinFET has been introduced in the 22/16nm node to continue CMOS logic scaling. The very tight pitches foreseen for the coming generation necessitate the introduction of different scaling boosters. In this paper, we review how these elements affect the analog device performance. The benefits of alternative channel material for dedicated RF applications and the related integration challenges are also discussed.

AB - FinFET has been introduced in the 22/16nm node to continue CMOS logic scaling. The very tight pitches foreseen for the coming generation necessitate the introduction of different scaling boosters. In this paper, we review how these elements affect the analog device performance. The benefits of alternative channel material for dedicated RF applications and the related integration challenges are also discussed.

UR - https://www.scopus.com/pages/publications/85056540155

U2 - 10.1109/ESSDERC.2018.8486857

DO - 10.1109/ESSDERC.2018.8486857

M3 - Chapter

AN - SCOPUS:85056540155

T3 - European Solid-State Device Research Conference

SP - 158

EP - 161

BT - 2018 48th European Solid-State Device Research Conference, ESSDERC 2018

PB - Editions Frontieres

Y2 - 3 September 2018 through 6 September 2018

ER -

Scaling CMOS beyond Si FinFET: An analog/RF perspective

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this