Scaling embedded EEPROMs for the integration in deep submicron technologies

Applications such as systems-on-chip and memory cards require embedded code storage at increasingly small dimensions. In this work a study of scaling embedded EEPROM cells for the integration in deep submicron technologies is undertaken. A well-structured methodology will be proposed and applied to a number of different EEPROM cell types that have been integrated successfully in submicron CMOS processes to date. When scaling embedded nonvolatile memories it is difficult to generate accurate scaling laws or general rules because the performance targets and operating requirements of the memory cells are strongly dependent on the application and process technology in which they are to be integrated. It is possible to generate rules that are application or process technology specific, but it is the aim here to evaluate the scaling of these embedded EEPROMs without a particular application or process technology in mind.