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Scaling low power embedded flash EEPROMs to 0.18um

  • R. Duffy
  • , A. Concannon
  • , A. Mathewson
  • , M. Slotboom
  • , D. Dormans
  • , N. Wils
  • , R. Verhaar

Research output: Chapter in Book/Report/Conference proceedingsConference proceedingpeer-review

Abstract

In this paper issues for the scaling of embedded flash EEPROMs for the integration in a O.18J.Lm CMOS process are discussed. It is shown that critical tradeoffs between process variables, operating conditions and cell size complicate the scaling procedure. However, through the application of a suitable simulation methodology, limiting factors can be identified and analysed and thus these tradeoffs can be resolved efficiently. O.18J.Lm CMOS process runs with the embedded flash EEPROM option have been successfully completed and devices have been measured and characterised.

Original languageEnglish
Title of host publicationESSDERC 1999 - Proceeding of the 29th European Solid-State Device Research Conference
EditorsR.P. Mertens, H. Grunbacher, H.E. Maes, G. Declerck
PublisherIEEE Computer Society
Pages620-623
Number of pages4
ISBN (Electronic)2863322451, 9782863322451
Publication statusPublished - 1999
Event29th European Solid-State Device Research Conference, ESSDERC 1999 - Leuven, Belgium
Duration: 13 Sep 199915 Sep 1999

Publication series

NameEuropean Solid-State Device Research Conference
Volume13-15 Sept. 1999
ISSN (Print)1930-8876

Conference

Conference29th European Solid-State Device Research Conference, ESSDERC 1999
Country/TerritoryBelgium
CityLeuven
Period13/09/9915/09/99

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