Semiconductor nanowire fabrication by bottom-up and top-down paradigms

Semiconductor nanowires have been the subject of intensive research investment over the past few decades. Their physical properties afford them applications in a vast network of active microelectronic research fields, including logic device scaling in very large scale integrated circuits, sensor devices, and energy harvesting. A range of routes to semiconductor nanowire production have opened up as a result of advances in nanowire fabrication techniques over the last number of decades. These nanowire fabrication routes can usually be categorized into one of two paradigms, bottom-up or top-down. Microelectronic systems typically rely on integrated device platforms, where each device and component thereof can be individually addressed. This requirement for precise addressability places significant demands on the mode of fabrication, specifically with regard to device definition, placement and density, which have typically been strengths of top-down fabrication processes. However, in recent years, advances in bottom-up fabrication processes have opened up the possibility of a synergy between bottom-up and top-down processes to achieve the benefits of both. This review article highlights the important considerations required for the continued advancement of semiconductor nanowire fabrication with a focus on the application of semiconductor nanowire fabrication for next-generation field-effect transistor devices.