Statistical characterization of 0.18 μm low-power CMOS process using efficient parameter extraction

K. G. McCarthy; E. V. Saavedra Diaz; D. B.M. Klaassen; A. Mathewson

Statistical characterization of 0.18 μm low-power CMOS process using efficient parameter extraction

K. G. McCarthy
, E. V. Saavedra Diaz
, D. B.M. Klaassen
, A. Mathewson

School of Engineering and Architecture

University College Cork

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper illustrates the use of an efficient parameter extraction strategy for MOS Model 9 to perform a statistical analysis of sample devices from a 0.18μm CMOS process. The parameter extraction strategy allows all the parameters for a particular device geometry to be extracted from just 50 measurements. These parameters are subsequently used with Principal Component Analysis to provide best-case or worst-case model sets or as inputs to a Monte-Carlo experiment to investigate some of the performance trade-offs of the process.

Original language	English
Pages	127-131
Number of pages	5
Publication status	Published - 1998
Event	Proceedings of the 1998 IEEE International Conference on Microelectronic Test Structures - Kanazawa, Jpn Duration: 23 Mar 1998 → 26 Mar 1998

Conference

Conference	Proceedings of the 1998 IEEE International Conference on Microelectronic Test Structures
City	Kanazawa, Jpn
Period	23/03/98 → 26/03/98

Cite this

@conference{26f349169b7540389f450da692ab9914,

title = "Statistical characterization of 0.18 μm low-power CMOS process using efficient parameter extraction",

abstract = "This paper illustrates the use of an efficient parameter extraction strategy for MOS Model 9 to perform a statistical analysis of sample devices from a 0.18μm CMOS process. The parameter extraction strategy allows all the parameters for a particular device geometry to be extracted from just 50 measurements. These parameters are subsequently used with Principal Component Analysis to provide best-case or worst-case model sets or as inputs to a Monte-Carlo experiment to investigate some of the performance trade-offs of the process.",

author = "McCarthy, \{K. G.\} and \{Saavedra Diaz\}, \{E. V.\} and Klaassen, \{D. B.M.\} and A. Mathewson",

year = "1998",

language = "English",

pages = "127--131",

note = "Proceedings of the 1998 IEEE International Conference on Microelectronic Test Structures ; Conference date: 23-03-1998 Through 26-03-1998",

}

Statistical characterization of 0.18 μm low-power CMOS process using efficient parameter extraction. / McCarthy, K. G.; Saavedra Diaz, E. V.; Klaassen, D. B.M. et al.
1998. 127-131 Paper presented at Proceedings of the 1998 IEEE International Conference on Microelectronic Test Structures, Kanazawa, Jpn.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Statistical characterization of 0.18 μm low-power CMOS process using efficient parameter extraction

AU - McCarthy, K. G.

AU - Saavedra Diaz, E. V.

AU - Klaassen, D. B.M.

AU - Mathewson, A.

PY - 1998

Y1 - 1998

N2 - This paper illustrates the use of an efficient parameter extraction strategy for MOS Model 9 to perform a statistical analysis of sample devices from a 0.18μm CMOS process. The parameter extraction strategy allows all the parameters for a particular device geometry to be extracted from just 50 measurements. These parameters are subsequently used with Principal Component Analysis to provide best-case or worst-case model sets or as inputs to a Monte-Carlo experiment to investigate some of the performance trade-offs of the process.

AB - This paper illustrates the use of an efficient parameter extraction strategy for MOS Model 9 to perform a statistical analysis of sample devices from a 0.18μm CMOS process. The parameter extraction strategy allows all the parameters for a particular device geometry to be extracted from just 50 measurements. These parameters are subsequently used with Principal Component Analysis to provide best-case or worst-case model sets or as inputs to a Monte-Carlo experiment to investigate some of the performance trade-offs of the process.

UR - https://www.scopus.com/pages/publications/0031640039

M3 - Paper

AN - SCOPUS:0031640039

SP - 127

EP - 131

T2 - Proceedings of the 1998 IEEE International Conference on Microelectronic Test Structures

Y2 - 23 March 1998 through 26 March 1998

ER -

Statistical characterization of 0.18 μm low-power CMOS process using efficient parameter extraction

Abstract

Conference

Other files and links

Fingerprint

Cite this