Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition

L. Witters; F. Sebaai; A. Hikavyy; A. P. Milenin; R. Loo; A. De Keersgieter; G. Eneman; T. Schram; K. Wostyn; K. Devriendt; A. Schulze; R. Lieten; S. Bilodeau; E. Cooper; P. Storck; C. Vrancken; H. Arimura; P. Favia; E. Vancoille; J. Mitard; R. Langer; A. Opdebeeck; F. Holsteyns; N. Waldron; K. Barla; V. De Heyn; D. Mocuta; N. Collaert

doi:10.23919/VLSIT.2017.7998168

Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition

L. Witters
, F. Sebaai
, A. Hikavyy
, A. P. Milenin
, R. Loo
, A. De Keersgieter
, G. Eneman
, T. Schram
, K. Wostyn
, K. Devriendt
, A. Schulze
, R. Lieten
, S. Bilodeau
, E. Cooper
, P. Storck
, C. Vrancken
, H. Arimura
, P. Favia
, E. Vancoille
, J. Mitard

R. Langer, A. Opdebeeck, F. Holsteyns, N. Waldron, K. Barla, V. De Heyn, D. Mocuta, N. Collaert

Interuniversitair Micro-Elektronica Centrum
Entegris, Inc.
Siltronic AG

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (L_g=40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic control at the shortest gate lengths studied (L_g=40nm) with DIBL of 30mV/V and sub-threshold slope (SS_sat) of 79mV/dec. This work shows a significant improvement not only compared to our previous work on strained Ge finFETs but also when benchmarked to published Ge GAA devices.

Original language	English
Title of host publication	2017 Symposium on VLSI Technology, VLSI Technology 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	T194-T195
ISBN (Electronic)	9784863486058
DOIs	https://doi.org/10.23919/VLSIT.2017.7998168
Publication status	Published - 31 Jul 2017
Externally published	Yes
Event	37th Symposium on VLSI Technology, VLSI Technology 2017 - Kyoto, Japan Duration: 5 Jun 2017 → 8 Jun 2017

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	37th Symposium on VLSI Technology, VLSI Technology 2017
Country/Territory	Japan
City	Kyoto
Period	5/06/17 → 8/06/17

Keywords

gate-all-around
groundplane doping
nanowire
strain relaxed buffer
strained germanium

Access to Document

10.23919/VLSIT.2017.7998168

Cite this

Witters, L., Sebaai, F., Hikavyy, A., Milenin, A. P., Loo, R., De Keersgieter, A., Eneman, G., Schram, T., Wostyn, K., Devriendt, K., Schulze, A., Lieten, R., Bilodeau, S., Cooper, E., Storck, P., Vrancken, C., Arimura, H., Favia, P., Vancoille, E., ... Collaert, N. (2017). Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition. In 2017 Symposium on VLSI Technology, VLSI Technology 2017 (pp. T194-T195). Article 7998168 (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2017.7998168

Witters, L. ; Sebaai, F. ; Hikavyy, A. et al. / Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition. 2017 Symposium on VLSI Technology, VLSI Technology 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. T194-T195 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{ac49eee90efc41989ef152d8dfc7e532,

title = "Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition",

abstract = "Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (Lg=40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic control at the shortest gate lengths studied (Lg=40nm) with DIBL of 30mV/V and sub-threshold slope (SSsat) of 79mV/dec. This work shows a significant improvement not only compared to our previous work on strained Ge finFETs but also when benchmarked to published Ge GAA devices.",

keywords = "gate-all-around, groundplane doping, nanowire, strain relaxed buffer, strained germanium",

author = "L. Witters and F. Sebaai and A. Hikavyy and Milenin, \{A. P.\} and R. Loo and \{De Keersgieter\}, A. and G. Eneman and T. Schram and K. Wostyn and K. Devriendt and A. Schulze and R. Lieten and S. Bilodeau and E. Cooper and P. Storck and C. Vrancken and H. Arimura and P. Favia and E. Vancoille and J. Mitard and R. Langer and A. Opdebeeck and F. Holsteyns and N. Waldron and K. Barla and \{De Heyn\}, V. and D. Mocuta and N. Collaert",

note = "Publisher Copyright: {\textcopyright} 2017 JSAP.; 37th Symposium on VLSI Technology, VLSI Technology 2017 ; Conference date: 05-06-2017 Through 08-06-2017",

year = "2017",

month = jul,

day = "31",

doi = "10.23919/VLSIT.2017.7998168",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "T194--T195",

booktitle = "2017 Symposium on VLSI Technology, VLSI Technology 2017",

address = "United States",

}

Witters, L, Sebaai, F, Hikavyy, A, Milenin, AP, Loo, R, De Keersgieter, A, Eneman, G, Schram, T, Wostyn, K, Devriendt, K, Schulze, A, Lieten, R, Bilodeau, S, Cooper, E, Storck, P, Vrancken, C, Arimura, H, Favia, P, Vancoille, E, Mitard, J, Langer, R, Opdebeeck, A, Holsteyns, F, Waldron, N, Barla, K, De Heyn, V, Mocuta, D & Collaert, N 2017, Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition. in 2017 Symposium on VLSI Technology, VLSI Technology 2017., 7998168, Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., pp. T194-T195, 37th Symposium on VLSI Technology, VLSI Technology 2017, Kyoto, Japan, 5/06/17. https://doi.org/10.23919/VLSIT.2017.7998168

Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition. / Witters, L.; Sebaai, F.; Hikavyy, A. et al.
2017 Symposium on VLSI Technology, VLSI Technology 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. T194-T195 7998168 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

TY - GEN

T1 - Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition

AU - Witters, L.

AU - Sebaai, F.

AU - Hikavyy, A.

AU - Milenin, A. P.

AU - Loo, R.

AU - De Keersgieter, A.

AU - Eneman, G.

AU - Schram, T.

AU - Wostyn, K.

AU - Devriendt, K.

AU - Schulze, A.

AU - Lieten, R.

AU - Bilodeau, S.

AU - Cooper, E.

AU - Storck, P.

AU - Vrancken, C.

AU - Arimura, H.

AU - Favia, P.

AU - Vancoille, E.

AU - Mitard, J.

AU - Langer, R.

AU - Opdebeeck, A.

AU - Holsteyns, F.

AU - Waldron, N.

AU - Barla, K.

AU - De Heyn, V.

AU - Mocuta, D.

AU - Collaert, N.

PY - 2017/7/31

Y1 - 2017/7/31

N2 - Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (Lg=40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic control at the shortest gate lengths studied (Lg=40nm) with DIBL of 30mV/V and sub-threshold slope (SSsat) of 79mV/dec. This work shows a significant improvement not only compared to our previous work on strained Ge finFETs but also when benchmarked to published Ge GAA devices.

AB - Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (Lg=40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic control at the shortest gate lengths studied (Lg=40nm) with DIBL of 30mV/V and sub-threshold slope (SSsat) of 79mV/dec. This work shows a significant improvement not only compared to our previous work on strained Ge finFETs but also when benchmarked to published Ge GAA devices.

KW - gate-all-around

KW - groundplane doping

KW - nanowire

KW - strain relaxed buffer

KW - strained germanium

UR - https://www.scopus.com/pages/publications/85028068496

U2 - 10.23919/VLSIT.2017.7998168

DO - 10.23919/VLSIT.2017.7998168

M3 - Conference proceeding

AN - SCOPUS:85028068496

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - T194-T195

BT - 2017 Symposium on VLSI Technology, VLSI Technology 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 37th Symposium on VLSI Technology, VLSI Technology 2017

Y2 - 5 June 2017 through 8 June 2017

ER -

Witters L, Sebaai F, Hikavyy A, Milenin AP, Loo R, De Keersgieter A et al. Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition. In 2017 Symposium on VLSI Technology, VLSI Technology 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. T194-T195. 7998168. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSIT.2017.7998168

Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition

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Keywords

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