@inproceedings{ac49eee90efc41989ef152d8dfc7e532,
title = "Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition",
abstract = "Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (Lg=40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic control at the shortest gate lengths studied (Lg=40nm) with DIBL of 30mV/V and sub-threshold slope (SSsat) of 79mV/dec. This work shows a significant improvement not only compared to our previous work on strained Ge finFETs but also when benchmarked to published Ge GAA devices.",
keywords = "gate-all-around, groundplane doping, nanowire, strain relaxed buffer, strained germanium",
author = "L. Witters and F. Sebaai and A. Hikavyy and Milenin, \{A. P.\} and R. Loo and \{De Keersgieter\}, A. and G. Eneman and T. Schram and K. Wostyn and K. Devriendt and A. Schulze and R. Lieten and S. Bilodeau and E. Cooper and P. Storck and C. Vrancken and H. Arimura and P. Favia and E. Vancoille and J. Mitard and R. Langer and A. Opdebeeck and F. Holsteyns and N. Waldron and K. Barla and \{De Heyn\}, V. and D. Mocuta and N. Collaert",
note = "Publisher Copyright: {\textcopyright} 2017 JSAP.; 37th Symposium on VLSI Technology, VLSI Technology 2017 ; Conference date: 05-06-2017 Through 08-06-2017",
year = "2017",
month = jul,
day = "31",
doi = "10.23919/VLSIT.2017.7998168",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "T194--T195",
booktitle = "2017 Symposium on VLSI Technology, VLSI Technology 2017",
address = "United States",
}