Structural and electrical analysis of thin interface control layers of MgO or Al₂O₃ deposited by atomic layer deposition and incorporated at the high-k/III-V interface of MO₂/In _xGa_1-xAs (M = Hf|Zr, x= 0|0.53) gate stacks

Control of the high-k/III-V interface by deposition of thin (∼1-2 nm) interface control layers (ICLs) of Al₂O₃ or MgO, as part of an overall bi-layer structure with a high-k metal oxide MO₂ (M = Hf|Zr), is explored. An Al₂O₃ or MgO ICL is deposited on untreated In_xGa_1-xAs (x = 0|0.53) substrates prior to MO₂ gate oxide deposition, forming a Pd/high-k/ICL/III-V gate stack. The aim of a bi-layer structure is to enable continued device scaling using a high-k MO₂ oxide while improving the high-k/III-V interface quality and interfacial band structure, with an Al₂O₃ or MgO ICL. Metal-oxide-semiconductor capacitor (MOSCAP) devices with an Al ₂O₃ ICL on p-type GaAs display significantly reduced leakage current density, and reduced frequency dispersion of accumulation capacitance when compared to a device with no ICL, indicating an improved high-k/III-V band structure and interface quality, respectively. Further studies on ZrO₂/Al₂O₃/n-In_0.53Ga _0.47As devices reveal a reduced defect response with a post-metal forming gas anneal.