TY - CHAP
T1 - Survey of low power testing of VLSI circuits
AU - Basker, P.
AU - Arulmurugan, A.
PY - 2012
Y1 - 2012
N2 - The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. Low power dissipation during test application is becoming increasingly important in today's VLSI systems design and is a major goal in the future development of VLSI design.
AB - The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. Low power dissipation during test application is becoming increasingly important in today's VLSI systems design and is a major goal in the future development of VLSI design.
KW - DFT-BIST-LFSR-CUT-ATPG
UR - https://www.scopus.com/pages/publications/84858721387
U2 - 10.1109/ICCCI.2012.6158884
DO - 10.1109/ICCCI.2012.6158884
M3 - Chapter
AN - SCOPUS:84858721387
SN - 9781457715822
T3 - 2012 International Conference on Computer Communication and Informatics, ICCCI 2012
BT - 2012 International Conference on Computer Communication and Informatics, ICCCI 2012
T2 - 2012 International Conference on Computer Communication and Informatics, ICCCI 2012
Y2 - 10 January 2012 through 12 January 2012
ER -