Synthesizing testable systolic arrays

M. A. Evans; W. P. Marnane

Synthesizing testable systolic arrays

M. A. Evans
, W. P. Marnane

Bangor University

Research output: Contribution to conference › Paper › peer-review

Abstract

The testability of a design can be assessed subjectively using estimates and a scoring system. Objective assessment requires a Test Vector Generation (TVG) effort as well as Design for Test (DFT) hardware changes. However assessing the testability of different systolic arrays which implement the same algorithm can contain a large TVG cost. We develop an integrated design and test methodology for systolic arrays, which generates a set of test vectors early in the design cycle, thus eliminating the TVG cost from the design evaluation. Hence testability can be considered alongside traditional design considerations such as performance.

Original language	English
Pages	61-72
Number of pages	12
Publication status	Published - 1996
Externally published	Yes
Event	Proceedings of the 1994 3rd International Conference on the Economics of Design, Test, and Manufacturing - Austin, TX, USA Duration: 16 May 1994 → 17 May 1994

Conference

Conference	Proceedings of the 1994 3rd International Conference on the Economics of Design, Test, and Manufacturing
City	Austin, TX, USA
Period	16/05/94 → 17/05/94

Cite this

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title = "Synthesizing testable systolic arrays",

abstract = "The testability of a design can be assessed subjectively using estimates and a scoring system. Objective assessment requires a Test Vector Generation (TVG) effort as well as Design for Test (DFT) hardware changes. However assessing the testability of different systolic arrays which implement the same algorithm can contain a large TVG cost. We develop an integrated design and test methodology for systolic arrays, which generates a set of test vectors early in the design cycle, thus eliminating the TVG cost from the design evaluation. Hence testability can be considered alongside traditional design considerations such as performance.",

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AU - Marnane, W. P.

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N2 - The testability of a design can be assessed subjectively using estimates and a scoring system. Objective assessment requires a Test Vector Generation (TVG) effort as well as Design for Test (DFT) hardware changes. However assessing the testability of different systolic arrays which implement the same algorithm can contain a large TVG cost. We develop an integrated design and test methodology for systolic arrays, which generates a set of test vectors early in the design cycle, thus eliminating the TVG cost from the design evaluation. Hence testability can be considered alongside traditional design considerations such as performance.

AB - The testability of a design can be assessed subjectively using estimates and a scoring system. Objective assessment requires a Test Vector Generation (TVG) effort as well as Design for Test (DFT) hardware changes. However assessing the testability of different systolic arrays which implement the same algorithm can contain a large TVG cost. We develop an integrated design and test methodology for systolic arrays, which generates a set of test vectors early in the design cycle, thus eliminating the TVG cost from the design evaluation. Hence testability can be considered alongside traditional design considerations such as performance.

UR - https://www.scopus.com/pages/publications/0029707128

M3 - Paper

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EP - 72

T2 - Proceedings of the 1994 3rd International Conference on the Economics of Design, Test, and Manufacturing

Y2 - 16 May 1994 through 17 May 1994

ER -

Synthesizing testable systolic arrays

Abstract

Conference

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