Temperature effects on trigate SOI MOSFETs

Jean Pierre Colinge; Liam Floyd; Aidan J. Quinn; Gareth Redmond; John C. Alderman; W. Xiong; C. Rinn Cleavelin; T. Schulz; Klaus Schruefer; Gerhard Knoblinger; Paul Patruno

doi:10.1109/LED.2006.869941

Temperature effects on trigate SOI MOSFETs

Jean Pierre Colinge
, Liam Floyd
, Aidan J. Quinn
, Gareth Redmond
, John C. Alderman
, W. Xiong
, C. Rinn Cleavelin
, T. Schulz
, Klaus Schruefer
, Gerhard Knoblinger
, Paul Patruno

Research output: Contribution to journal › Article › peer-review

Abstract

Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6 × 10¹⁷ cm^-3. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO₂ interfaces, shows up at temperatures lower than 150 K.

Original language	English
Pages (from-to)	172-174
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	27
Issue number	3
DOIs	https://doi.org/10.1109/LED.2006.869941
Publication status	Published - Mar 2006

Keywords

Cryogenic electronics
MOSFETs
Quantum wires
Semiconductor device measurements
Silicon-on-insulator (SOI) technology

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10.1109/LED.2006.869941

Cite this

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title = "Temperature effects on trigate SOI MOSFETs",

abstract = "Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6 × 1017 cm-3. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO2 interfaces, shows up at temperatures lower than 150 K.",

keywords = "Cryogenic electronics, MOSFETs, Quantum wires, Semiconductor device measurements, Silicon-on-insulator (SOI) technology",

author = "Colinge, \{Jean Pierre\} and Liam Floyd and Quinn, \{Aidan J.\} and Gareth Redmond and Alderman, \{John C.\} and W. Xiong and Cleavelin, \{C. Rinn\} and T. Schulz and Klaus Schruefer and Gerhard Knoblinger and Paul Patruno",

year = "2006",

month = mar,

doi = "10.1109/LED.2006.869941",

language = "English",

volume = "27",

pages = "172--174",

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TY - JOUR

T1 - Temperature effects on trigate SOI MOSFETs

AU - Colinge, Jean Pierre

AU - Floyd, Liam

AU - Quinn, Aidan J.

AU - Redmond, Gareth

AU - Alderman, John C.

AU - Xiong, W.

AU - Cleavelin, C. Rinn

AU - Schulz, T.

AU - Schruefer, Klaus

AU - Knoblinger, Gerhard

AU - Patruno, Paul

PY - 2006/3

Y1 - 2006/3

N2 - Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6 × 1017 cm-3. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO2 interfaces, shows up at temperatures lower than 150 K.

AB - Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6 × 1017 cm-3. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO2 interfaces, shows up at temperatures lower than 150 K.

KW - Cryogenic electronics

KW - MOSFETs

KW - Quantum wires

KW - Semiconductor device measurements

KW - Silicon-on-insulator (SOI) technology

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U2 - 10.1109/LED.2006.869941

DO - 10.1109/LED.2006.869941

M3 - Article

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SN - 0741-3106

VL - 27

SP - 172

EP - 174

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 3

ER -

Temperature effects on trigate SOI MOSFETs

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Keywords

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