Abstract
Three test chips that can be used to evaluate IC packaging technologies either at the development stage or as process control tools in a manufacturing environment is described. Structures have been incorporated in the test chips for the characterization of packaging technologies in terms of their environmental and mechanical reliability, thermal resistance, and electrical performance. The author describes the potential application of the test chips in a manufacturing environment for process control of die-attach material and of moisture content in hermetic package sealing. The application of one of the test chips to electrical characterization of high-pin-count packaging technologies is presented.
| Original language | English |
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| Pages | 286-289 |
| Number of pages | 4 |
| Publication status | Published - 1989 |
| Event | Sixth IEEE/CHMT International Electronic Manufacturing Technology Symposium - Nara, Japan Duration: 26 Apr 1989 → 28 Apr 1989 |
Conference
| Conference | Sixth IEEE/CHMT International Electronic Manufacturing Technology Symposium |
|---|---|
| City | Nara, Japan |
| Period | 26/04/89 → 28/04/89 |
