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Test structure for electrical characterization of copper nanowire anisotropic conductive film (NW-ACF) for 3D stacking applications

Research output: Chapter in Book/Report/Conference proceedingsConference proceedingpeer-review

Abstract

Copper nanowire arrays (∼200 nm diameter) grown in porous polymer template is a potential low temperature interconnection technology compared to metal/metal or solder micro-bump interconnects for 3D chip stacking. To advance this technology, good understanding of material and process related electrical properties is required. In this paper, a stacked test chip module with copper daisy chain pattern, which is finished by ∼1 μm indium bonding layer, has been designed to extract the resistance and capacitance data of the NW-ACF.

Original languageEnglish
Title of host publication2014 IEEE International Conference on Microelectronic Test Structures, ICMTS 2014 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages165-169
Number of pages5
ISBN (Print)9781479921928
DOIs
Publication statusPublished - 2014
Event27th International Conference on Microelectronic Test Structures, ICMTS 2014 - Udine, Italy
Duration: 24 Mar 201427 Mar 2014

Publication series

NameIEEE International Conference on Microelectronic Test Structures

Conference

Conference27th International Conference on Microelectronic Test Structures, ICMTS 2014
Country/TerritoryItaly
CityUdine
Period24/03/1427/03/14

Keywords

  • 3D chip stack
  • Capacitance
  • Interconnection resistance
  • Leakage current
  • NW-ACF (Nanowire Anisotropic Conductive Film)
  • Thermocompression bonding

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