Testing a motion estimator array

The authors examine the problems of testing a motion estimator array using a novel strategy for testing VLSI regular arrays. They present a case study to demonstrate the ability of the strategy to test regular arrays with data restrictions, to test large word level arrays, and to test less regular arrays. The motion estimator array is considered as an array within an array. Each processing element is a bit-sliced array where the bit slice contains three different cells. Each of the constituent cells in the bit slice is exhaustively tested, resulting in a high fault coverage. The vectors which test the processing element (PE) can then be propagated to every PE in the word level array. Since the data buses are 8 b wide, the propagation graphs developed for the bit-level arrays are not suitable for this word level array. A suitable change in notation is presented.