@inbook{088299420e4745d7ac949484147a3cec,
title = "TESTING BIT-LEVEL SYSTOLIC ARRAYS.",
abstract = "A computational approach to generating test patterns for systolic arrays is presented and illustrated through the example of a two-dimensional bit-level array with counter-flow data. The approach uses regular propagating test sequences, extending the concepts of pI-testability and C-testability of combinational logic arrays. The computational approach is shown to cope well with the complexity of testing systolic arrays and to provide a very useful computer-aided-design tool.",
author = "Marnane, \{W. P.\} and Moore, \{W. R.\} and Yassine, \{H. M.\} and E. Gautrin and N. Burgess and McCabe, \{A. P.H.\}",
year = "1987",
language = "English",
isbn = "081860798X",
series = "Digest of Papers - International Test Conference",
publisher = "IEEE",
pages = "906--914",
booktitle = "Digest of Papers - International Test Conference",
note = "Dig Pap Int Test Conf 1987, Proc, Integr of Test with Des and Manuf ; Conference date: 01-09-1987 Through 03-09-1987",
}