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TESTING BIT-LEVEL SYSTOLIC ARRAYS.
W. P. Marnane
, W. R. Moore
, H. M. Yassine
, E. Gautrin
, N. Burgess
, A. P.H. McCabe
University of Oxford
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Engineering
Systolic Array
100%
Testability
66%
Two Dimensional
33%
Design Tool
33%
Computer Aided Design
33%
Test Sequence
33%
Counterflow
33%