Testing of VLSI regular arrays

W. P. Marnane; W. R. Moore

Testing of VLSI regular arrays

W. P. Marnane
, W. R. Moore

University of Oxford

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

The authors present a unifying approach to testing fine-grained VLSI arrays. The approach covers a wide range of regular arrays and leads directly to test pattern generation. This method can meet the requirements of any single-cell fault model and can cope with restricted access to the boundary of the array. It is shown how existing concepts such as C-testability can be utilized in generating test patterns.

Original language	English
Title of host publication	1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc
Publisher	Publ by IEEE
Pages	145-148
Number of pages	4
ISBN (Print)	0818608722
Publication status	Published - 1988
Externally published	Yes

Publication series

Name	1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc

Cite this

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abstract = "The authors present a unifying approach to testing fine-grained VLSI arrays. The approach covers a wide range of regular arrays and leads directly to test pattern generation. This method can meet the requirements of any single-cell fault model and can cope with restricted access to the boundary of the array. It is shown how existing concepts such as C-testability can be utilized in generating test patterns.",

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AB - The authors present a unifying approach to testing fine-grained VLSI arrays. The approach covers a wide range of regular arrays and leads directly to test pattern generation. This method can meet the requirements of any single-cell fault model and can cope with restricted access to the boundary of the array. It is shown how existing concepts such as C-testability can be utilized in generating test patterns.

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M3 - Chapter

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SN - 0818608722

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BT - 1988 IEEE Int Conf Comput Des VLSI Comput Process ICCD 88 Proc

PB - Publ by IEEE

ER -

Testing of VLSI regular arrays

Abstract

Publication series

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