Abstract
The authors present a unifying approach to the testing of fine-grained VLSI arrays. The approach covers a wide range of regular arrays and leads directly to test pattern generation. It includes the often overlooked but nontrivial problem of observing the fault effects, especially at the edges of the arrays. The problems and possible solutions are illustrated using the example of a systolic correlator.
| Original language | English |
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| Pages | 304-311 |
| Number of pages | 8 |
| Publication status | Published - 1989 |
| Externally published | Yes |
| Event | Proceedings of the 1st European Test Conference - Paris, France Duration: 12 Apr 1989 → 14 Apr 1989 |
Conference
| Conference | Proceedings of the 1st European Test Conference |
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| City | Paris, France |
| Period | 12/04/89 → 14/04/89 |