The comparison and combination of CMOS inductor Q-enhancement techniques

  • O. Murphy
  • , J. Blackburn
  • , P. Murphy
  • , K. McCarthy
  • , A. Murphy

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

Much emphasis and blame has been placed on integrated silicon inductors and their poor Q values, leading to degradation in circuit performance, especially at RF and microwave frequencies. This is no more evident than in WLAN applications at 5.25 GHz where poor Q values can induce increased noise figure, power consumption and linearity deterioration. This paper will present a concise comparison of non-invasive Q-enhancement techniques using patterned ground shields, stacked metal, thick copper and differential inductors. A differential stacked metal inductor with patterned ground shield will also be demonstrated for its effectiveness.

Original languageEnglish
Title of host publication2003 High Frequency Postgraduate Student Colloquium
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages94-97
Number of pages4
ISBN (Electronic)0780381238
DOIs
Publication statusPublished - 2003
Event2003 High Frequency Postgraduate Student Colloquium - Belfast, Ireland
Duration: 8 Sep 20039 Sep 2003

Publication series

NameIEEE High Frequency Postgraduate Student Colloquium
Volume2003-January
ISSN (Print)1546-6523

Conference

Conference2003 High Frequency Postgraduate Student Colloquium
Country/TerritoryIreland
CityBelfast
Period8/09/039/09/03

Keywords

  • Circuit optimization
  • CMOS technology
  • Degradation
  • Energy consumption
  • Inductors
  • Microwave frequencies
  • Noise figure
  • Radio frequency
  • Silicon
  • Wireless LAN

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